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1999 data sheet mos integrated circuit m pd17230,17231,17232,17233,17234,17235,17236 description m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 (hereafter called m pd17236 subseries) are 4-bit single- chip microcontrollers for small general-purpose infrared remote control transmitters. it employs a 17k architecture of general-purpose register type devices for the cpu, and can directly execute operations between memories instead of the conventional method of executing operations through the accumulator. moreover, all the instructions are 16-bit 1-word instructions which can be programmed efficiently. in addition, a one-time prom model, m pd17p236 note , to which data can be written only once, is also available. it is convenient either for evaluating the m pd17236 subseries programs or small-scale production of application systems. note under development detailed functions are described in the following manual. be sure to read this manual when designing your system. m pd172 subseries user's manual: u12795e features ? infrared remote controller carrier generator circuit (rem output) ? 17k architecture: general-purpose register system ? program memory (rom), data memory (ram) m pd17230 m pd17231 m pd17232 m pd17233 m pd17234 m pd17235 m pd17236 program 4 k bytes 8 k bytes 12 k bytes 16 k bytes 20 k bytes 24 k bytes 32 k bytes memory (rom) (2048 16) (4096 16) (6144 16) (8192 16) (10240 16) (12288 16) (16384 16) data memory 223 4 bits (ram) ? 8-bit timer : 1 channel ? basic internal timer/watchdog timer : 1 channel ? instruction execution time (can be changed in two steps) at f x = 4 mhz : 4 m s (high-speed mode)/8 m s (ordinary mode) at f x = 8 mhz : 2 m s (high-speed mode)/4 m s (ordinary mode) ? external interrupt pin (int) : 1 ? i/o pins : 21 ? supply voltage : v dd = 2.2 to 3.6 v (at f x = 8 mhz (high-speed mode)) v dd = 2.0 to 3.6 v (at f x = 4 mhz (high-speed mode)) ? low-voltage detector circuit (mask option) unless otherwise specified, the m pd17236 is treated as the representative model throughout this document. document no. u14360ej1v0ds00 (1st edition) date published july 1999 n cp (k) printed in japan 4-bit single-chip microcontroller for small general-purpose infrared remote control transmitter the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 2 application preset remote controllers, toys, portable systems, etc. ordering information part number package m pd17230mc- -5a4 30-pin plastic shrink sop (300 mil) m pd17231mc- -5a4 30-pin plastic shrink sop (300 mil) m pd17232mc- -5a4 30-pin plastic shrink sop (300 mil) m pd17233mc- -5a4 30-pin plastic shrink sop (300 mil) m pd17234mc- -5a4 30-pin plastic shrink sop (300 mil) m pd17235gt- 28-pin plastic sop (375 mil) m pd17235mc- -5a4 30-pin plastic shrink sop (300 mil) m pd17236gt- 28-pin plastic sop (375 mil) m pd17236mc- -5a4 30-pin plastic shrink sop (300 mil) remark indicates rom code suffix. difference between m pd17236 subseries and m pd17225 subseries item m pd17236 subseries m pd17225 subseries rom capacity m pd17230: 2048 16 bits m pd17225: 2048 16 bits m pd17231: 4096 16 bits m pd17226: 4096 16 bits m pd17232: 6144 16 bits m pd17227: 6144 16 bits m pd17233: 8192 16 bits m pd17228: 8192 16 bits m pd17234: 10240 16 bits m pd17235: 12288 16 bits m pd17236: 16384 16 bits port p0b 0 -p0b 3 : i/o (bit i/o) p0b 0 -p0b 3 : input p0c 0 -p0c 3 : i/o (group i/o) p0c 0 -p0c 3 : output p0d 0 -p0d 3 : i/o (group i/o) p0d 0 -p0d 3 : output p1a 0 : input or output selectable by mask option reset reset pin is internally pulled down by low level is output from wdout pin by ? reset by watchdog timer occurrence of the internal reset signals on the occurrence of the internal reset signals on the ? reset by stack pointer left, and reset takes place (usually, reset pin left, and reset takes place if the wdout pin ? low-voltage detection is pulled up). is externally connected to the reset pin. circuit (mask option) stop mode release <1> when any of pins p0a 0 -p0a 3 goes low when any of p0a 0 -p0a 3 or p0b 0 -p0b 3 goes condition <2> when p0b 0 -p0b 3 , p0c 0 -p0c 3 , and low p0d 0 -p0d 3 are used as input pins and any of them goes low <3> when the interrupt request (irq) of an interrupt for which ip flag is set is generated at rising or falling edge of int pin carrier frequency selected by mask option 7.8 khz to 1 mhz (f x = 4 mhz) <1> if carrier generation clock (rf x ) is f x /2: 7.8 khz to 1 mhz <2> if carrier generation clock (rf x ) is f x : 15.6 khz to 2 mhz pin 14 p1a 0 pin wdout pin
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 3 pin configuration (top view) ? 28-pin plastic sop (375 mil) m pd17235gt- , 17236gt- p0d 2 p0d 3 int p0e 0 p0e 1 p0e 2 p0e 3 rem v dd x out x in gnd reset p1a 0 p0d 1 p0d 0 p0c 3 p0c 2 p0c 1 p0c 0 p0b 3 p0b 2 p0b 1 p0b 0 p0a 3 p0a 2 p0a 1 p0a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 4 gnd : ground ic1, ic2 : internally connected int : external interrupt request signal input p0a 0 -p0a 3 : input port (cmos input) p0b 0 -p0b 3 : input/output port (cmos input/n-ch open-drain output) p0c 0 -p0c 3 : input/output port (cmos input/n-ch open-drain output) p0d 0 -p0d 3 : input/output port (cmos input/n-ch open-drain output) p0e 0 -p0e 3 : input/output port (cmos push-pull output) p1a 0 : input port (cmos input/n-ch open-drain output) note rem : remote controller output (cmos push-pull output) reset : reset input v dd : power supply x in , x out : resonator connection note input or output is selected by mask option. ? 30-pin plastic shrink sop (300 mil) m pd17230mc- -5a4, m pd17231mc- -5a4, m pd17232mc- -5a4, m pd17233mc- -5a4, m pd17234mc- -5a4, m pd17235mc- -5a4, m pd17236mc- -5a4 p0d 2 p0d 3 int p0e 0 p0e 1 p0e 2 p0e 3 rem v dd x out x in gnd reset p1a 0 ic1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ic2 p0d 1 p0d 0 p0c 3 p0c 2 p0c 1 p0c 0 p0b 3 p0b 2 p0b 1 p0b 0 p0a 3 p0a 2 p0a 1 p0a 0
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 5 block diagram note input or output selectable by mask option. p0a 0 p0a 1 p0a 2 p0a 3 p0b 0 p0c 0 p0d 0 p0e 0 p0b 1 p0c 1 p0d 1 p0e 1 p0b 2 p0c 2 p0d 2 p0e 2 p0b 3 p0c 3 p0d 3 p0e 3 p0a p0b p0c p0d p0e rf system reg. alu remote control divider rem int 8-bit timer interrupt controller v dd gnd x in x out instruction decoder program counter stack (5 levels) basic interval/ watchdog timer power supply circuit cpu clock osc 223 4 bits ram pd17230 : 2048 16 bits pd17231 : 4096 16 bits pd17232 : 6144 16 bits pd17233 : 8192 16 bits pd17234 : 10240 16 bits pd17235 : 12288 16 bits pd17236 : 16384 16 bits rom m m m m reset reset controller m m m p1a 0 note p1a
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 6 contents 1. pin functions .......................................................................................................................... 8 1.1 pin function list ............................................................................................................... 8 1.2 input/output circuits ........................................................................................................ 10 1.3 processing of unused pins ............................................................................................. 11 2. memory space ......................................................................................................................... 12 2.1 program counter (pc) ...................................................................................................... 12 2.2 program memory (rom) .................................................................................................. 15 2.3 stack ............................................................................................................................... .... 17 2.4 data memory (ram) .......................................................................................................... 19 2.5 register file (rf) .............................................................................................................. 26 3. ports ............................................................................................................................... ........... 29 3.1 port 0a (p0a 0 through p0a 3 ) ........................................................................................... 29 3.2 port 0b (p0b 0 through p0b 3 ) ........................................................................................... 29 3.3 port 0c (p0c 0 through p0c 3 ) ........................................................................................... 29 3.4 port 0d (p0d 0 through p0d 3 ) ........................................................................................... 29 3.5 port 0e (p0e 0 through p0e 3 ) ............................................................................................ 30 3.6 port 1a (p1a 0 ) .................................................................................................................... 30 3.7 int pin ............................................................................................................................... .31 3.8 switching bit i/o ............................................................................................................... 32 3.9 selecting i/o mode of group i/o ..................................................................................... 34 3.10 specifying pull-up resistor connection ....................................................................... 35 4. clock generator circuit ................................................................................................. 36 4.1 instruction execution time (cpu clock) selection ..................................................... 36 5. 8-bit timer and remote controller carrier generator circuit .................. 37 5.1 configuration of 8-bit timer (with modulo function) ................................................... 37 5.2 function of 8-bit timer (with modulo function) ........................................................... 39 5.3 carrier generator circuit for remote controller ......................................................... 41 6. basic interval timer/watchdog timer ........................................................................ 46 6.1 source clock for basic interval timer ........................................................................... 46 6.2 controlling basic interval timer ..................................................................................... 46 6.3 operation timing for watchdog timer .......................................................................... 48 7. interrupt functions ........................................................................................................... 49 7.1 interrupt sources .............................................................................................................. 49 7.2 hardware of interrupt control circuit ............................................................................ 50 7.3 interrupt sequence ........................................................................................................... 53 8. standby functions ............................................................................................................... 55 8.1 halt mode ......................................................................................................................... 55 8.2 halt instruction execution conditions ........................................................................ 56
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 7 8.3 stop mode ........................................................................................................................ 57 8.4 stop instruction execution conditions ........................................................................ 58 8.5 releasing standby mode ................................................................................................. 58 9. reset ............................................................................................................................... ........... 59 9.1 reset by reset signal input ............................................................................................ 59 9.2 reset by watchdog timer (with reset pin internally pulled down) ....................... 59 9.3 reset by stack pointer (with reset pin internally pulled down) ............................ 60 10. low-voltage detector circuit (with reset pin internally pulled down) ................................................................. 61 11. assembler reserved words ........................................................................................... 62 11.1 mask option directives .................................................................................................... 62 11.2 reserved symbols ............................................................................................................ 63 12. instruction set ..................................................................................................................... 70 12.1 instruction set outline ..................................................................................................... 70 12.2 legend ............................................................................................................................... .71 12.3 list of instruction sets .................................................................................................... 72 12.4 assembler (ra17k) built-in macro instruction ............................................................ 74 13. electrical specifications ................................................................................................ 75 14. application circuit example ........................................................................................... 81 15. package drawings .............................................................................................................. 82 16. recommended soldering conditions .......................................................................... 84 appendix a. differences between m pd17236 and m pd17p236 ...................................... 85 appendix b. functional comparison of m pd17236 subseries related products ....................................................................... 86 appendix c. development tools ........................................................................................... 88
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 8 1. pin functions 1.1 pin function list (1/2) pin no. symbol function output form on reset 27 (28) p0d 0 these pins constitute a 4-bit i/o port which can be set in the input n-ch low-level 28 (29) p0d 1 or output mode in 4-bit units (group i/o). open-drain output 1 (1) p0d 2 in the input mode, these pins serve as cmos input pins with a 2 (2) p0d 3 pull-up resistor, and can be used as key return input lines of a key matrix. the standby status must be released when at least one of the input lines goes low. in the output mode, these pins are used as n-ch open-drain output pins and can be used as the output lines of a key matrix. 3 (3) int external interrupt request signal. this signal releases the standby C input status if an external interrupt request signal is input to it when the int pin interrupt enable flag (ip) is set. 4 (4) p0e 0 these pins constitute a 4-bit i/o port that can be set in the input or cmos input 5 (5) p0e 1 output mode in 1-bit units. push-pull 6 (6) p0e 2 in the output mode, this port functions as a high current cmos 7 (7) p0e 3 output port. in the input mode, function as cmos input and can be specified to connect pull-up resistor by program. 8 (8) rem outputs transfer signal for infrared remote controller. cmos low-level active-high output. push-pull output 9 (9) v dd power supply C C 10 (10) x out connects ceramic resonator for system clock oscillation C (oscillation 11 (11) x in stops) 12 (12) gnd ground C C 13 (13) reset turns on pull down resistor if poc or watchdog timer overflows C input and if the stack pointer overflows or underflows, and resets the system. usually, the pull-down resistor is on. 14 (14) p1a 0 this can be set in the input or output mode by mask option. C input in the input mode, it serves as a cmos input pin. however, it (input) cannot release the stop mode. in the output mode, this pin functions as an n-ch open-drain output n-ch high- pin and can be used as an output line for a key matrix. open-drain impedance (output) output 15 (16) p0a 0 these pins are cmos input pins with a 4-bit pull-up resistor. C input 16 (17) p0a 1 they can be used as the key return input lines of a key matrix. 17 (18) p0a 2 if any one of these pins goes low, the standby status is released. 18 (19) p0a 3 19 (20) p0b 0 these pins constitute a 4-bit i/o port that can be set in the input or n-ch input 20 (21) p0b 1 output mode in 1-bit units. open-drain 21 (22) p0b 2 in the input mode, these pins are cmos input pins with a pull-up 22 (23) p0b 3 resistor, and can be used as the key return input lines of a key matrix. the standby status is released when at least one of these pins goes low. in the output mode, they serve as n-ch open-drain output pins and can be used as the output lines of a key matrix. remark the number in parenthesis in the pin no. column indicates the pin numbers of the 30-pin plastic ssop.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 9 1.1 pin function list (2/2) pin no. symbol function output form on reset 23 (24) p0c 0 these pins constitute a 4-bit i/o port that can be set in the input or n-ch low-level 24 (25) p0c 1 output mode in 4-bit units (group i/o). open-drain output 25 (26) p0c 2 in the input mode, these pins are cmos input pins with a pull-up 26 (27) p0c 3 resistor, and can be used as the key return input lines of a key matrix. the standby status is released when at least one of these pins goes low. in the output mode, they serve as n-ch open-drain output pins and can be used as the output lines of a key matrix. (15) ic1 these pins cannot be used. C C (30) ic2 leave open. remark the number in parenthesis in the pin no. column indicates the pin numbers of the 30-pin plastic ssop.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 10 1.2 input/output circuits the equivalent input/output circuit for each m pd17236 pin is shown below. (1) p0a v dd input buffer (2) p0b, p0c, p0d v dd p-ch n-ch output latch selector data output disable input buffer (3) p0e v dd data data p-ch p-ch n-ch v dd input buffer output disable pull-up register output latch selector (4) p1a (mask option) input buffer (mask option) output latch n-ch data (mask option) (mask option) remark ? when set to input by mask option sw: off, sw: on ? when set to output by mask option sw: on, sw: off (5) reset v dd p-ch reset input n-ch input buffer schmitt trigger input with hysteresis characteristics (6) int input buffer schmitt trigger input with hysteresis characteristics (7) rem data p-ch n-ch v dd output disable
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 11 1.3 processing of unused pins process the unused pins as follows: table 1-1. processing of unused pins pin recommended connection p0a 0 -p0a 3 leave unconnected. p0b 0 -p0b 3 p0c 0 -p0c 3 p0d 0 -p0d 3 p0e 0 -p0e 3 input: individually connect to v dd or gnd via resistor. output: leave unconnected. p1a 0 connect to gnd. rem leave unconnected. int connect to gnd. ic1, ic2 these pins cannot be used. leave unconnected.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 12 2. memory space 2.1 program counter (pc) the program counter (pc) specifies an address of the program memory (rom). the program counter is an 11/12/13-bit binary counter and a 1-bit segment counter (sgr) as shown in figure 2-1. its contents are initialized to address 0000h at reset. figure 2-1. configuration of program counter 2.1.1 segment register (sgr) the segment register specifies a segment of the program memory. table 2-1 shows the relation between the segment register and program memory. table 2-1. relation between segment register and program memory value of segment register segment of program memory 0 segment 0 1 segment 1 the segment register is set when the following instructions are executed: ? br @ar ? call @ar ? syscal entry page pc ( pd17230) msb lsb sgr pc 12 pc 11 pc 10 pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 m pc ( pd17231) m pc ( pd17232, 17233) m pc ( pd17234, 17235, 17236) m
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 13 the first address of the subroutine that can be called by the system call instruction (syscal entry) is the first 16 steps of each block (block 0 to 7) in page 0 of segment 1 (system segment). figure 2-2. outline of system call instruction page 1 page 2 page 3 page 0 (16 bits 2k steps) (16 bits 8k steps) segment 0 page 1 page 2 page 3 (16 bits 8k steps) segment 1 (system segment) block 0 block 1 block 2 block 7 block 0 of segment 1 entry address of syscal instruction 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 7 f 7 f 8 0 8 0 f f f f 0 0 0 0 f f f f 0 0 0 0 h h h h h h h h 0 0 0 0 0 0 0 0 2 2 3 3 2 3 3 2 7 f 7 f 8 0 8 0 f f f f 0 0 0 0 f f f f 0 0 0 0 h h h h h h h h 020ffh 02100h 021ffh 02200h 022ffh 02700h 02000h 0200fh area in which entry address of system segment can be specified . . . .
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 14 figure 2-3. value of program counter on execution of each instruction note m pd17230 : b 0 through b 10 m pd17231 : b 0 through b 11 m pd17232, 17233 : b 0 through b 12 m pd17234, 17235, 17236 : b 0 through b 12 , sgr remark entry h : high-order 3 bits of entry entry l : low-order 4 bits of entry table 2-2. interrupt vector address priority internal/external interrupt source vector address 1 internal 8-bit timer 0003h 2 external rising and falling edges of int pin 0002h 3 internal basic interval timer 0001h contents of program counter (pc) note sgr 1 0 0 b 12 0 0 1 1 0 0 0 b 11 0 1 0 1 0 0 0 b 10 0 b 9 0 b 8 0 b 7 0 0 b 6 0 0 b 5 0 0 b 4 0 0 b 3 0 b 2 0 b 1 0 b 0 0 program counter instruction br addr call addr syscal entry br @ar call @ar movt dbf, @ar ret retsk reti other instructions (including skip instruction) on acknowledging interrupt watchdog timer reset, reset pin, reset by stack pointer page 0 page 1 page 2 page 3 entry l entry h operand of instruction (addr) operand of instruction (addr) contents of address register re- tained re- tained contents (return address) of address stack register (asr) specified by stack pointer (sp) vector address of each interrupt increment re- tained
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 15 2.2 program memory (rom) the configuration of the program memory is as follows: part number program memory capacity program memory address m pd17230 2048 16 bits 0000h-07ffh m pd17231 4096 16 bits 0000h-0fffh m pd17232 6144 16 bits 0000h-17ffh m pd17233 8192 16 bits 0000h-1fffh m pd17234 10240 16 bits 0000h-27ffh m pd17235 12288 16 bits 0000h-2fffh m pd17236 16384 16 bits 0000h-3fffh the program memory stores a program, interrupt vector table, and fixed data table. the program memory is addressed by the program counter. figure 2-4 shows the program memory map. the entire range of the program memory can be addressed by the bd addr, br @ar, call @ar, movt dbf, and @ar instructions. note, however, that the subroutine entry addresses that can be specified by the call addr instruction are from 0000h to 07ffh.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 16 figure 2-4. program memory map ( pd17236) 16 bits h h branch addresses for br addr instruction branch addresses for br@ar instruction subroutine entry addresses for call@ar instruction table reference addresses for movt dbf, @ar instruction address h h h h h h h h h ( pd17235) reset start address basic interval timer interrupt vector int pin rising/falling edge interrupt vector 8-bit timer interrupt vector segment 0 page 0 page 1 page 2 page 3 page 0 page 1 page 2 page 3 subroutine entry address for call addr instruction subroutine entry address for call addr instruction branch addresses for br addr instruction segment 1 (system segment) 0 f 1 2 3 f f f f 0 f 0 f 0 0 0 f f f f 0 f 0 f 0 0 0 7 f 7 f 0 f 0 3 0 0 0 0 0 1 1 2 2 h f f 7 2 m ( pd17230) m ( pd17231) m ( pd17232) m ( pd17233) m ( pd17234) m m
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 17 2.3 stack a stack is a register to save a program return address and the contents of system registers (to be described later) when a subroutine is called or when an interrupt is accepted. 2.3.1 stack configuration figure 2-5 shows the stack configurarion. a stack consists of a stack pointer (a 4-bit binary counter, the high-order 1 bit fixed to 0), five 11-bit ( m pd17230)/ 12-bit ( m pd17231)/13-bit ( m pd17232, 17233)/14-bit ( m pd17234, 17235, 17236) address stack registers, and three 6-bit interrupt stack registers. figure 2-5. stack configuration address stack registers (asr) b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 address stack register 1 address stack register 2 address stack register 3 address stack register 4 b 2 b 1 b 0 spb 2 spb 1 spb 0 stack pointer (sp) 0h 1h 2h 3h 4h 5h 6h 7h 0h 1h 2h interrupt stack registers (intsk) banksk1 banksk2 bcdsk0 bcdsk1 bcdsk2 cmpsk0 cmpsk1 cmpsk2 cysk0 cysk1 cysk2 zsk0 zsk1 zsk2 ixesk0 ixesk1 ixesk2 address stack register 0 the reset pin is internally pulled down and reset is effected. b 3 0 b 12 pd17231 pd17232, 17233 pd17234, 17235, 17236 b 4 b 3 b 2 b 5 banksk0 b 1 b 0 m m m undefined undefined undefined b 13 pd17230 m
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 18 2.3.2 function of stack the address stack register stores a return address when the subroutine call instruction or table reference instruction (first instruction cycle) is executed or when an interrupt is accepted. it also stores the contents of the address registers (ars) when a stack manipulation instruction (push ar) is executed. if subroutines or interrupts are nested to more than 5 levels, the reset pin is internally pulled down and a reset is effected. the interrupt stack register (intsk) saves the contents of the bank register (bank) and program status word (psword) when an interrupt is accepted. the saved contents are restored when an interrupt return (reti) instruction is executed. intsk saves data each time an interrupt is accepted, but the data stored first is lost if more than 3 levels of interrupts occur . 2.3.3 stack pointer (sp) and interrupt stack pointer table 2-3 shows the operations of the stack pointer (sp). the stack pointer can take eight values, 0h-07. because there are only five stack registers available, however, the reset pin is internally pulled down and reset is effected if the value of sp is 6 or greater . table 2-3. operations of stack pointer instruction value of stack pointer (sp) counter of interrupt stack register call addr call @ar movt dbf, @ar C1 0 (1st instruction cycle) push ar syscal entry when interrupt is accepted C1 C1 ret retsk movt dbf, @ar +1 0 (2nd instruction cycle) pop ar reti +1 +1
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 19 2.4 data memory (ram) data memory (random access memory) stores data for operations and control. it can be read-/write-accessed by instructions. 2.4.1 memory configuration figure 2-6 shows the configuration of the data memory (ram). the data memory consists of two banks: bank0 and bank1. in each bank, every 4 bits of data is assigned an address. the high-order 3 bits of the address indicate a row address and the low-order 4 bits of the address indicate a column address. for example, a data memory location indicated by row address 1h and column address 0ah is termed a data memory location at address 1ah. each address stores data of 4 bits (= a nibble). in addition, the data memory is divided into following six functional blocks: (1) system register (sysreg) a system register (sysreg) is resident on addresses 74h to 7fh (12 nibbles long) of each bank. in other nibbles, each bank has a system register at its addresses 74h to 7fh. (2) data buffer (dbf) a data buffer is resident on addresses 0ch to 0fh (4 nibbles long) of bank 0 of data memory. the reset value is 0320h. (3) general register (gr) a general register is resident on any row (16 nibbles long) of any bank of data memory. the row address of the general register is pointed by the general pointer (rp) in the system register (sysreg). (4) port register a port data register is resident on addresses 6fh, and 70h to 73h (5 nibbles) of bank0 of data memory. no data can be written to or read from the addresses 71h to 73h of bank1.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 20 (5) general-purpose data memory the general-purpose data memory area is an area of the data memory excluding the system register area, and the port register areay? this memory area has a total of 223 nibbles (111 nibbles in bank0 and 112 nibbles in bank1). figure 2-6. configuration of data memory 0123456789abcdef 0 1 2 3 4 5 6 7 bank 0 0123456789abcdef bank 1 system register (sysreg) example address 1ah in bank 0 system register (sysreg) row address row address column address data buffer (dbf) p0a p0b p0c p0d p0e column address 0 1 2 3 4 5 6 7 p1a note 2 note 1 notes 1. address 6fh of bank 1 can be used as a general-purpose data memory area. 2. only bit 0 of address 70h of bank 1 is used. bits 1 through 3 are fixed to 0. caution no data can be written to or read from the addresses 71h to 73h of bank1.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 21 2.4.2 system registers (sysreg) the system registers are registers that are directly related to control of the cpu. these registers are mapped to addresses 74h-7fh on the data memory and can be referenced regardless of bank specification. the system registers include the following registers: ? address registers (ar0-ar3) ? window register (wr) ? bank register (bank) ? memory pointer enable flag (mpe) ? memory pointers (mph, mpl) ? index registers (ixh, ixm, ixl) ? general register pointers (rph, rpl) ? program status word (psword) figure 2-7. configuration of system register b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh ar 3 ar 2 ar 1 ar 0 wr bank ixh ixm ixl rph rpl psw mph mpl address register (ar) window register (wr) bank register (bank) data memory row address pointer (mp) index register (ix) general register pointer (rp) program status word (psword) 000 00 00 00 m p e b c d c m p c yz i x e (rp) (ix) (mp) (bank) data bit symbol name address initial value at reset 0000000000000000 0000000000000000000000000000 undefined 0 0 0 (wr) (ar) ( pd17232,17233) (ar) ( pd17231) (ar) ( pd17230) m 00000 0000 m m 00 (ar) ( pd17234,17235,17236) m
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 22 2.4.3 general register (gr) a general register is a 16-word register on the data memory and used for arithmetic operations and transfer of data to and from the data memory. (1) configuration of general register figure 2-8 shows the configuration of the general register. a general register occupies 16 nibbles (16 4 bits) on a selected row address of the data memory as shown in figure 2-6. the row address is selected by the general register pointer (rp) of the system register. the rp having four significant bits can point to any row address in the range of 0h to 7h of each bank (bank0 and bank1). (2) functions of the general register the general register enables an arithmetic operation and data transfer between the data memory and a selected general register by a single instruction. as a general register is a part of the data memory, you can say that the general register enables arithmetic operation and data transfer between two locations of the data memory. similarly, the general register can be accessed by a data memory manipulation instruction as it is a part of the data memory. figure 2-8. configuration of general registers (rp) rph rpl b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 0 1001 1 1010 2 1011 3 1100 4 1101 5 1110 6 1111 7 0123456789abcdef rp system registers port register general registers (16 nibbles) general register pointer bank0 bank1 column address general register settable range f i x e d t o 0 a s s i g n e d t o b c d f l a g ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? system registers example general registers when rp = 0000010b ? same system registers exist f i x e d t o 0 f i x e d t o 0 port regis- ter
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 23 2.4.4 data buffer (dbf) the data buffer on the addresses 0ch to 0fh of data memory is used for data transfer to and from peripheral hardware and for storage of data during table reference. (1) functions of the data buffer the data buffer has two major functions: a function to transfer to and from hardware and a function to read constant data from the program memory (for table reference). figure 2-9 shows the relationship between the data buffer and peripheral hardware. figure 2-9. data buffer and peripheral hardware data buffer (dbf) internal bus program memory (rom) constant data peripheral address peripheral hardware 8-bit timer (tmc, tmm) carrier generator for remote controller (nrzltmm, nrzhtmm) address register (ar) 05h, 06h 03h, 04h 40h
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 24 table 2-4. relations between hardware peripherals and data buffer hardware peripheral register transferring data with data buffer peripherals name symbol peripheral address data buffer used put/get 8-bit timer 8-bit counter tmc 05h dbf0, dbf1 get only 8-bit modulo tmm 06h dbf0, dbf1 put only register remote controller nrz low-level nrzltmm 03h dbf0, dbf1 put carrier generator timer modulo get register nrz high-level nrzhtmm 04h dbf0, dbf1 put (clear bit 3 timer modulo of dbf1 to 0) register get (bits 3 of dbf1 is always 0) address register address register ar 40h dbf0-dbf3 put note 1 get note 2 notes 1. in the m pd17230: bits 0 to 3 of ar3 and bit 3 of ar2 are any, in the m pd17231: bits 0 to 3 of ar3 are any, in the m pd17232, 17233: bits 1 to 3 of ar3 are any, in the m pd17234, 17235, 17236: bits 2 to 3 of ar3 are any 2. in the m pd17230: bits 0 to 3 of ar3 and bit 3 of ar2 are always 0, in the m pd17231: bits 0 to 3 of ar3 are always 0, in the m pd17232, 17233: bits 1 to 3 of ar3 are always 0, in the m pd17234, 17235, 17236: bits 2 to 3 of ar3 are always 0 (2) table reference a movt instruction reads constant data from a specified location of the program memory (rom) and sets it in the data buffer. the function of the movt instruction is explained below. movt dbf, @ar: reads data from a program memory location pointed to by the address register (ar) and sets it in the data buffer (dbf). dbf 3 dbf 2 dbf 1 dbf 0 movt dbf, @ ar b 15 b 0 16 bits program memory (rom) data buffer
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 25 (3) note on using data buffer when transferring data to/from the peripheral hardware via the data buffer, the unused peripheral addresses, write-only peripheral registers (only when executing put), and read-only peripheral registers (only when executing get) must be handled as follows: ? when device operates nothing changes even if data is written to the read-only register. if the unused address is read, an undefined value is read. nothing changes even if data is written to that address. ? using assembler an error occurs if an instruction is executed to read a write-only register. again, an error occurs if an instruction is executed to write data to a read-only register. an error also occurs if an instruction is executed to read or write an unused address. ? if an in-circuit emulator (ie-17k or ie-17k-et) is used (when instruction is executed for patch processing) an undefined value is read if an attempt is made to read the data of a write-only register, but an error does not occur. nothing changes even if data is written to a read-only register, and an error does not occur. an undefined value is read if an unused address is read; nothing changes even if data is written to this address. an error does not occur.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 26 2.5 register file (rf) the register file mainly consists of registers that set the conditions of the peripheral hardware. these registers can be controlled by dedicated instructions peek and poke, and the embedded macro instructions of ra17k, setn, clrn, and initflg. 2.5.1 configuration of register file figure 2-10 shows the configuration of the register file and how the register file is accessed by the peek and poke instructions. the control registers are controlled by using dedicated instructions peek and poke. since the control registers are assigned to addresses 00h-3fh regardless of the bank, the addresses 00h-3fh of the general-purpose data memory cannot be accessed when the peek or poke instruction is used. the addresses that can be accessed by the peek and poke instructions are the addresses 00h-3fh of the control registers and 40h-7fh of the general-purpose data memory. the register file consists of these addresses. the control registers are assigned to addresses 80h-bfh on the ie-17k to facilitate debugging. figure 2-10. register file access with peek or poke instructions 0123456789abcdef 0 1 2 3 4 5 6 7 column address row address data memory system register 0 1 2 3 peek wr, sp poke lcdmd, wr poke m063, wr control register register file
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 27 2.5.2 control registers the control registers consists of a total of 64 nibbles (64 x 4 bits) of the addresses 00h-3fh of the register file. of these, however, only 16 nibbles are actually used. the remaining 48 nibbles are unused registers that are inhibited from being read or written. when the peek wr, rf instruction is executed, the contents of the register file addressed by rf are read to the window register. when the poke rf, wr instruction is executed, the contents of the window register are written to the register file addressed by rf. when using the assembler (ra17k), the macro instructions listed below, which are embedded as flag type symbol manipulation instructions, can be used. the macro instructions allow the contents of the register file to be manipulated in bit units. for the configuration of the control register, refer to figure 11-1 register file list . setn : sets flag to 1 clrn : sets flag to 0 sktn : skips if all flags are 1 skfn : skips if all flags are 0 notn : complements flag initflg : initializes flag initflgx : initalizes flag 2.5.3 notes on using register files when using the register files, bear in mind the points described below. for details, refer to m pd172xx subseries users manual (u12795e) . (1) when manipulating control registers (read-only and unused registers) when manipulating the write-only (w), the read-only (r) and unused control registers by using the assembler or in-circuit emulator, keep in mind the following points: ? when device operates nothing changes even if data is written to the read-only register. if the unused register is read, an undefined value is read; nothing is changed even if data is written to this register. ? using assembler an error occurs if instruction is excecuted to read data to the write-only register. an error occurs if an instruction is executed to write data to the read-only register. an error also occurs if an instruction is executed to read or write the unused address. ? when an in-circuit emulator (ie-17k or ie-17k-et) is used (when instruction is executed for patch processing) an undefined value is read if the write-only register is read, and an error does not occur. nothing changes even if data is written to the read-only register, and an error does not occur. an undefined value is read if the unused address is read; nothing changes even if data is written to this address. an error does not occur.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 28 (2) symbol definition of register file an error occurs if a register file address is directly specified as a numeral by the operand rf of the peek wr, rf or poke rf, wr instruction if the 17k series assembler (ra17k) is being used. therefore, the addresses of the register file must be defined in advance as symbols. to define the addresses of the control registers as symbols, define them as the addresses 80h-bfh of bank0. the portion of the register file overlapping the data memory (40h-7fh), however, can be defined as symbols as is.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 29 3. ports 3.1 port 0a (p0a 0 through p0a 3 ) this is a 4-bit input port. data is read through port register p0a (address 70h of bank0). this port is a cmos input port with a pull-up resistor, and can be used for key return input for a key matrix. in the standby mode, the standby status is released when a low level is input to at least one of these pins. 3.2 port 0b (p0b 0 through p0b 3 ) this is a 4-bit i/o port which can be set in the input or output mode in 1-bit units by using p0bbio (address 26h) of the register file. in the input mode, each bit of this port serves as a cmos input pin with a pull-up resistor and can be used as a key return input line of a key matrix. in the standby mode, the standby status is released when a low level is input to at least one of these pins. in the output mode, these pins serve as n-ch open-drain output pins and can be used as key source lines of a key matrix. the data input to this port can be read or the data output from this port can be set by using the p0b register (address 71h of bank0). when this port is read in the output mode, the contents of the output latch are read. in the input mode, a pull-up resistor of 200 k w is connected to each bit of this port. in the output mode, the pull- up resistor is disconnected. on reset, this port is set in the input mode. 3.3 port 0c (p0c 0 through p0c 3 ) this is a 4-bit i/o port which can be set in the input or output mode in 4-bit units (group i/o) by using p0cdgio (bit 2 of address 37h) of the register file. in the input mode, each bit of this port serves as a cmos input pin with a pull-up resistor and can be used as a key return input line of a key matrix. in the standby mode, the standby status is released when a low level is input to at least one of these pins. in the output mode, these pins serve as n-ch open-drain output pins and can be used as key source lines of a key matrix. the data input to this port can be read or the data output from this port can be set by using the p0c register (address 72h of bank0). when this port is read in the output mode, the contents of the output latch are read. in the input mode, a pull-up resistor of 200 k w is connected to each bit of this port. in the output mode, the pull- up resistor is disconnected. on reset, this port is set in the output mode and outputs low. 3.4 port 0d (p0d 0 through p0d 3 ) this is a 4-bit i/o port which can be set in the input or output mode in 4-bit units (group i/o) by using p0cdgio (bit 3 of address 37h) of the register file. in the input mode, each bit of this port serves as a cmos input pin with a pull-up resistor and can be used as a key return input line of a key matrix. in the standby mode, the standby status is released when a low level is input to at least one of these pins. in the output mode, these pins serve as n-ch open-drain output pins and can be used as key source lines of a key matrix. the data input to this port can be read or the data output from this port can be set by using the p0d register (address 73h of bank0). when this port is read in the output mode, the contents of the output latch are read. in the input mode, a pull-up resistor of 200 k w is connected to each bit of this port. in the output mode, the pull- up resistor is disconnected. on reset, this port is set in the output mode and outputs low.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 30 3.5 port 0e (p0e 0 through p0e 3 ) this is a 4-bit i/o port which can be set in the input or output mode in 1-bit units by the p0ebio (address 27h) of the register file. to read the input data or to set the output data, use the p0e register (address 6fh of bank0). when data is read in the output mode, the contents of the output latch are read. connection of a pull-up resistor can be specified in 1-bit units by the p0ebpu (address 17h) of the register file. (when the pull-up resistor is connected, note that the pull-up resistor is not disconnected even when the output mode is set.) on reset, this port is set in the input port. 3.6 port 1a (p1a 0 ) this port can be set in the input or output mode by mask option. in the input mode, this port serves as a cmos input port. the input data is read by using port register p1a (address 70h of bank1). this port cannot be used to release the stop mode. in the output mode, it serves as an n-ch open-drain output port and can be used as a key source line of a key matrix. the output data is set by using port register p1a (address 70h of bank1). when this port is read in the output mode, the contents of the output latch are read. on reset, this port goes into a high-impedance state.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 31 3.7 int pin this pin inputs an external interrupt request signal. at either the rising or falling edge of the signal input to this pin, the irq flag (rf: address 3eh, bit 0) is set. the status of this pin can be read by using the int flag (rf: address 0fh, bit 0). when the high level is input to the pin, the int flag is set to 1; when the low level is input, the flag is reset to 0 (refer to 7.2.1 int ). figure 3-1. relations between port register and each pin bank address target port bit output read contents written contents on reset format input mode output mode input mode output mode 0 70h port 0a b 3 p0a3 input pin status C C C input mode b 2 p0a2 (with pull-up b 1 p0a1 resistor) b 0 p0a0 71h port 0b b 3 p0b3 n-ch output latch output latch output latch b 2 p0b2 open drain b 1 p0b1 b 0 p0b0 72h port 0c b 3 p0c3 output mode b 2 p0c2 (low-level b 1 p0c1 output) b 0 p0c0 73h port 0d b 3 p0d3 b 2 p0d2 b 1 p0d1 b 0 p0d0 6fh port 0e b 3 p0e3 cmos input mode b 2 p0e2 push-pull (without pull- b 1 p0e1 up resistor) b 0 p0e0 1 70h port 1a b 0 p1a0 input C C C input mode (input/output (in input (without pull- mode set by mode) up resistor) mask option) n-ch C output latch output latch output latch output mode open drain (high- (in output impedance mode) output)
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 32 3.8 switching bit i/o the i/o which can be set in the input or output mode in bit units is called a bit i/o. p0b and p0e are bit i/o ports, which can be set in the input or output mode in bit units by the register file shown below. when the mode is changed from input to output, the p0b and p0e output latch contents are output to the port lines, as soon as the mode has been changed. 3210 p0bbio3 p0bbio2 p0bbio1 p0bbio0 address rf : 26h on reset 0h r/w r/w p0bbio0 0 1 sets p0b 0 input/output mode sets p0b 0 in input mode sets p0b 0 in output mode p0bbio1 0 1 sets p0b 1 input/output mode sets p0b 1 in input mode sets p0b 1 in output mode p0bbio2 0 1 sets p0b 2 input/output mode sets p0b 2 in input mode sets p0b 2 in output mode p0bbio3 0 1 sets p0b 3 input/output mode sets p0b 3 in input mode sets p0b 3 in output mode
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 33 32 10 p0ebio3 p0ebio2 p0ebio1 p0ebio0 address rf : 27h p0ebio0 on reset 0h r/w r/w 0 1 sets p0e 0 input/output mode sets p0e 0 in input mode sets p0e 0 in output mode p0ebio1 0 1 p0ebio2 0 1 p0ebio3 0 1 sets p0e 1 input/output mode sets p0e 1 in input mode sets p0e 1 in output mode sets p0e 2 input/output mode sets p0e 2 in input mode sets p0e 2 in output mode sets p0e 3 input/output mode sets p0e 3 in input mode sets p0e 3 in output mode
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 34 3.9 selecting i/o mode of group i/o an i/o that is set in the input or output mode in 4-bit units is called a group i/o. p0c and p0d can be used as group i/o ports. the input and output modes of these ports are selected by using the following register file. if the mode is changed from input to output, the contents of the port register are output to the respective ports as soon as the mode has been changed. 3210 p0dgio p0cgio 0 0 address rf : 37h on reset ch r/w r/w p0cgio 0 1 i/o mode of p0c 0 -p0c 3 sets p0c 0 -p0c 3 in input mode. sets p0c 0 -p0c 3 in output mode. p0dgio 0 1 i/o mode of p0d 0 -p0d 3 sets p0d 0 -p0d 3 in input mode. sets p0d 0 -p0d 3 in output mode.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 35 3.10 specifying pull-up resistor connection whether or not a pull-up resistor is connected to port p0e can be specified by the following registers of the register file in 1-bit units note . 32 10 p0ebpu3 p0ebpu2 p0ebpu1 p0ebpu0 address rf : 17h p0ebpu0 on reset 0h r/w r/w 0 1 connects pull-up resistor to p0e 0 p0ebpu1 0 1 p0ebpu2 0 1 p0ebpu3 0 1 not connected connected connects pull-up resistor to p0e 1 not connected connected connects pull-up resistor to p0e 2 not connected connected connects pull-up resistor to p0e 3 not connected connected note to disconnect the pull-up resistor in the output mode, clear the corresponding bit of the p0ebpu register.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 36 4. clock generator circuit 4.1 instruction execution time (cpu clock) selection the m pd17236 is equipped with a clock oscillator that supplies clocks to the cpu and hardware peripherals. instruction execution time can be changed in two steps (ordinary mode and high-speed mode) without changing the oscillation frequency. to change the instruction execution time, change the mode of sysck (rf: address 02h) of the register file by using the poke instruction. note, that the mode is actually only changed when the instruction next to the poke instruction has been executed. when using the high-speed mode, pay attention to the supply voltage. (refer to 13. electrical specifica- tions .) on reset, the ordinary mode is set. 32 10 0 0 0 sysck address rf : 02h sysck on reset 0h r/w r/w 0 1 selects instruction execution time ordinary mode 32/f x (8 s) m high-speed mode 16/f x (4 s) m figures in ( ): indicate figures when system clock f x = 4 mhz.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 37 5. 8-bit timer and remote controller carrier generator circuit the m pd17236 is equipped with the 8-bit timer which is mainly used to generate the leader pulse of the remote controller signal, and to output codes. 5.1 configuration of 8-bit timer (with modulo function) figure 5-1 shows the configuration of the 8-bit timer. as shown in this figure, the 8-bit timer consists of an 8-bit counter (tmc), an 8-bit modulo register (tmm), a comparator that compares the value of the timer with the value of the modulo register, and a selector that selects the operation clock of the 8-bit timer. to start/stop the 8-bit timer, and to reset the 8-bit counter, tmen (address 33h, bit 3) and tmres (address 33h, bit 2) of the register file are used. to select the operation clock of the 8-bit timer, use tmck1 (address 33h, bit 1) and tmck0 (address 33h, bit 0) of the register file. the value of the 8-bit counter is read by using the get instruction through dbf (data buffer). no value can be set to the 8-bit counter. a value is set to the modulo register by using the put instruction through dbf. the value of the modulo register cannot be read. when the value of the counter coincides with that of the modulo register, an interrupt flag (irqtm: address 3fh, bit 0) of the register file is set. 76543210 tmc tmm address on reset r/w peripheral register: 05h 00h r address on reset r/w peripheral register: 06h ffh w 8-bit counter 76543210 8-bit modulo register caution do not clear tmm to 0 (irqtm is not set).
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 38 figure 5-1. configuration of 8-bit timer and remote controller carrier generator circuit data buffer internal bus tmen tmres tmck1 tmck0 selector rf : 33h 8-bit timer remote controller carrier generator circuit f x /32 f x /64 f x /256 8-bit modulo register tmm comparator 8-bit counter tmc irqtm 7-bit counter f x /2 note comparator 7-bit modulo register nrzltmm 7-bit counter comparator 7-bit modulo register nrzhtmm r s q nrzbf nrz rf : 11h rf : 12h rem fixed 0 bit 7 bit 7 sw f x note note mask options. select either one of these. remark tmm, tmc, nrzltmm, and nrzhtmm are peripheral registers.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 39 5.2 function of 8-bit timer (with modulo function) notes 1. when the stop mode is released, bit 3 must be set. 2. bit 2 is a write-only bit. caution if the system clock is changed while the timer is counting, an error occurs in the timer as follows (when system clock f x = 4 mhz): ? high-speed mode 16/f x ? normal mode 32/f x ... (error due to resolution of set timer) +1.5 m s ? normal mode 32/f x ? high-speed mode 16/f x ... (error due to resolution of set timer) C1.5 m s 32 10 tmen tmres tmck1 tmck0 address rf : 33h tmres on reset 8h r/w r/w 0 1 8-bit timer reset flag data read out is always "0" resets 8-bit counter and irqtm tmen 0 1 8-bit timer count enable flag stops 8-bit timer count operation enable 8-bit timer count operation (falling edge) tmck1 tmck0 00 01 10 11 8-bit timer clock source selection count clock: f x /32 (measurable time range: 8 s to 2.048 ms, resolution: 8 s (error: +8 s)) m count clock: f x /64 (measurable time range: 16 s to 4.096 ms, resolution: 16 s (error: +16 s)) m count clock: f x /256 (measurable time range: 64 s to 16.384 ms, resolution: 64 s (error: +64 s)) m remote controller carrier generator circuit output (carrier output: 1 s to 128 s, resolution: 1 s) value indicated by parentheses is for when ( ): f (system clock) = f x = 4mhz sys note 1 note 2 m m m m m mm m m
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 40 nrzltmm address on reset r/w peripheral register: 03h undefined r/w 76543210 7-bit modulo register bit 7 0 1 output control of rem pin when nrz = 1, carrier output to rem pin when nrz = 1, high-level output to rem pin nrzhtmm address on reset r/w peripheral register: 04h undefined r/w 76543210 7-bit modulo register bit 7 fixed to 0 0
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 41 5.3 carrier generator circuit for remote controller m pd17236 is provided with a carrier generator circuit for the remote controller. the remote controller carrier generator circuit consists of a 7-bit counter, nrz high-level timer modulo register (nrzhtmm), and nrz low-level timer modulo register (nrzltmm). the high-level and low-level periods are set in the corresponding modulo registers through the dbf to determine the carrier duty factor and carrier frequency. either the system clock (f x ) divided by two or the original oscillation can be selected by mask option as an input to the 7-bit counter (where the clock for generating carrier is rf x ). when rf x is oscillated by a 4-mhz oscillator, therefore, the input clock is 2 mhz (f x /2) or 4 mhz (f x ). the nrz high-level output timer modulo register is called nrzhtmm, and the nrz low-level timer modulo register is called nrzltmm. data is written to these registers by the put instruction. the contents for these register are read by the get instruction. bit 7 of nrzltmm specifies whether the carrier or high level is output to the rem pin. to output the carrier, be sure to clear bit 7 to 0. 5.3.1 remote controller signal output control the rem pin, which outputs the carrier, is controlled by bits nrz and nrzbf for the register file and timer 0. while the nrz content is 1, the clock generated by the remote controller carrier generator circuit is output to the rem pin; while the nrz content is 0, the rem pin outputs a low level. the nrzbf content is automatically transferred to nrz by the interrupt signal generated by timer 0. if data is set in nrzbf in advance, the rem pin status changes in synchronization with the timer 0 counting operation. if the interrupt signal is generated from timer 0 with the rem pin at the high level, nrz being 1, and the carrier clock at the high level, the rem pin output is not in accordance with the updated content of nrz, until the carrier clock goes low. this processing is useful for holding the high level pulse width from the output carrier constant (refer to the figure below). when the content of nrz is 0, the remote controller carrier generator circuit stops. however, if the clock for timer 0 is output from the remote controller carrier generator circuit, the clock continues to operate, even when the nrz content becomes 0. an actual example showing a remote controller signal output to the rem pin is presented below.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 42 when bit 7 of nrzltmm is 0 (carrier output) nrz rem max. 500 ns (delay) note (f x = 4 mhz, rf x = f x /2) rem pin does not go low until carrier goes low even if nrz becomes 0 note value when (tmck1, tmck0) 1 (1, 1). when (tmck1, tmck0) = (1, 1), the value differs depending on how nrz is manipulated. if nrz is set by an instruction, the width of the first high-level pulse may be shortened. if nrz is set by data transferred from nrzbf, the high-level pulse is delayed by the low-level pulse of the carrier clock. when bit 7 of nrzltmm is 0 (carrier not output) 32 10 0 0 0 nrz address rf : 12h nrz on reset 0h r/w r/w 0 1 nrz data outputs low level to rem pin outputs a carrier to rem pin or high level output 32 10 0 0 0 nrzbf address rf : 11h nrzbf on reset 0h r/w r/w 0 1 nrz data output next nrz buffer bit. transfered to nrz by interrupt signal of timer 0. nrz rem
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 43 setting carrier frequency and duty factor where the system clock frequency is f x , carrier frequency is f c , and carrier generation clock is rf x : ? when rf x = f x /2: (division ratio) = f x /(2 f c ) ? when rf x = f x : (division ratio) = f x /f c is divided into m:n and is set in the modulo registers as follows: high-level period set value = { m/(m + n)} C 1 low-level period set value = { n/(m + n)} C 1 example where f c = 38 khz, duty factor (high-level period) = 1/3, f x = 4 mhz, and rf x = f x /2: = 4 mhz/(2 38 khz) = 52.6 m:n = 1:2 from the above, the value of the modulo register is: high-level period = 17 low-level period = 34 therefore, the carrier frequency is 37.74 khz. table 5-1. carrier frequency list (1) where f x = 4 mhz and rf x = f x /2 set value t h ( m s) t l ( m s) 1/f c ( m s) f c (khz) duty nrzhtmm nrzltmm 00h 00h 0.5 0.5 1.0 1000 1/2 01h 02h 1.0 1.5 2.5 400 2/5 04h 04h 2.5 2.5 5.0 200 1/2 09h 09h 5.0 5.0 10.0 100 1/2 0fh 10h 8.0 8.0 16.5 60.6 1/2 0fh 21h 8.0 17.0 25.0 40.0 1/3 11h 21h 9.0 17.0 26.0 38.5 1/3 11h 22h 9.0 17.5 26.5 37.7 1/3 19h 35h 13.0 27.0 40.0 25.0 1/3 3fh 3fh 32.0 32.0 64.0 15.6 1/2 7fh 7fh 64.0 64.0 120.0 7.8 1/2 . . . .
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 44 (2) where f x = 4 mhz, rf x = f x (original oscillation) set value t h ( m s) t l ( m s) 1/f c ( m s) f c (khz) duty nrzhtmm nrzltmm 00h 00h 0.25 0.25 0.5 2000 1/2 01h 02h 0.5 0.75 1.25 800 2/5 04h 04h 1.25 1.25 2.5 400 1/2 09h 09h 2.5 2.5 5.0 200 1/2 0fh 10h 4.0 4.25 8.25 121 1/2 0fh 21h 4.0 8.5 12.5 80 1/3 11h 21h 4.5 8.5 13.0 76.9 1/3 11h 22h 4.5 8.75 13.25 75.47 1/3 19h 35h 6.5 13.5 20.0 50 1/3 3fh 3fh 16.0 16.0 32.0 31.25 1/2 7fh 7fh 32.0 32.0 60.0 16.6 1/2 rem (f c ) t h t l 1/f c
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 45 5.3.2 countermeasures against noise during transmission (carrier output) when a signal is transmitted from the transmitter of a remote controller, a peak current of 0.5 to 1 a may flow through the infrared led. since two batteries are usually used as the power source of the transmitter, several w of equivalent resistance (r) exists in the power source as shown in figure 5-2. this resistance increases to 10 to 20 w if the supply voltage drops to 2 v. while the carrier is output from the rem pin (while the infrared led lights), therefore, a high- frequency noise may be generated on the power lines due to the voltage fluctuation that may take place especially during switching. to minimize the influence on the microcontroller of this high-frequency noise, take the following measures: <1> separate the power lines of the microcontroller from the power lines of the infrared led with the terminals of the batteries at the center. use thick power lines and keep the wiring short. <2> locate the resonator as close as possible to the microcontroller and shield it with gnd lines (as indicated by the shaded portion in the figure below). <3> locate the capacitor for stabilization of the power supply closely to the power lines of the microcontroller. also, use a capacitor to eliminate high-frequency noise. <4> to prevent data from changing, do not execute an interrupt that requires read/write processing and stack, such as key scan interrupt, and the call/ret instruction, while the carrier is output. <5> to improve the reliability in case of program hang-up, use the watchdog timer. figure 5-2. example of countermeasures against noise 0.5 to 1 a infrared led rem v dd microcomputer + r batteries v ss
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 46 6. basic interval timer/watchdog timer the basic interval timer has a function to generate the interval timer interrupt signal and watchdog timer reset signal. 6.1 source clock for basic interval timer the system clock (f x ) is divided, to generate the source clock for the basic interval timer. the input clock frequency for the basic interval timer is f x /2 7 . when the cpu is set in the stop mode, the basic interval timer also stops. 6.2 controlling basic interval timer the basic interval timer is controlled by the bits on the register file. that is, the basic interval timer is reset by btmres. the frequency for the interrupt signal, output by the basic interval timer, is selected by btmmd, and the watchdog timer is reset by wdtres. figure 6-1. basic interval timer configuration system clock f x 1/2 divider 7 1/2 divider 11 1/2 divider 1/2 divider 1/2 divider btmres wdtres btmck irqbtm reset signal output selector b f /2 18 x f /2 20 x
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 47 32 10 wdtres btmck btmres 0 address rf : 03h btmres on reset 0h r/w r/w note 0 1 basic interval timer reset data read out is always "0" writing "1" resets basic interval timer btmck 0 1 basic interval timer mode selection generates interrupt signal irqbtm every f x /2 20 wdtres 0 1 watchdog timer reset data read out is always "0" writing "1" resets watchdog timer (f x /2 21 counter) generates interrupt signal irqbtm every f x /2 18 note bits 1 and 3 are write-only bits.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 48 6.3 operation timing for watchdog timer the basic interval timer can be used as a watchdog timer. unless the watchdog timer is reset within a fixed time note , it judges that the program has hung up, and the m pd17236 is reset. it is therefore necessary to reset through programming the watchdog timer with in a fixed time. the watchdog timer can be reset by setting wdtres to 1. note fixed time: approx. 340 ms (at 4 mhz) caution the watchdog timer cannot be reset in the shaded range in figure 6-2. therefore, set wdtres before both the f x /2 21 and f x /2 20 signals go high. figure 6-2. watchdog timer operation timing f x /2 18 intbtm (f x /2 20 ) intbtm (f x /2 18 ) reset signal wdtres watchdog timer reset signal reset signal goes low if wdtres is not set setting wdtres at this timing is invalid f x /2 19 f x /2 20 f x /2 21
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 49 7. interrupt functions 7.1 interrupt sources m pd17236 is provided with three interrupt sources. when an interrupt has been accepted, the program execution automatically branches to a predetermined address, which is called a vector address. a vector address is assigned to each interrupt source, as shown in table 7-1. table 7-1. vector address priority interrupt source ext/int vector address 1 8-bit timer internal 0003h 2 int pin rising and falling edges external 0002h 3 basic interval timer internal 0001h when more than one interrupt request is issued at the same time, the interrupts are accepted in sequence, starting from the one with the highest priority. whether an interrupt is enabled or disabled is specified by the ei or di instruction. the basic condition under which an interrupt is accepted is that the interrupt is enabled by the ei instruction. while the di instruction is executed, or while an interrupt is accepted, the interrupt is disabled. to enable accepting an interrupt after the interrupt has been processed, the ei instruction must be executed before the reti instruction. accepting the interrupt is enabled by the ei instruction after the instruction next to the ei instruction has been executed. therefore, no interrupt can be accepted between the ei and reti instructions. caution in interrupt processing, only the bcd, cmp, cy, z, ixe flags are automatically saved to the stack by the hardware, to a maximum of three levels. also, within the interrupt processing contents, when peripheral hardware (timer, a/d converter, etc. ) is accessed, the dbf and wr contents are not saved by the hardware. accordingly, it is recommended that at the beginning of interrupt processing dbf and wr be saved by software to ram, and immediately before finishing interrupt processing the saved contents be returned to thier original location.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 50 7.2 hardware of interrupt control circuit this section describes the flags of the interrupt control circuit. (1) interrupt request flag and interrupt enable flag the interrupt request flag (irq ) is set to 1 when an interrupt request is generated, and is automatically cleared to 0 when the interrupt processing is excuted. an interrupt enable flag (ip ) is provided to each interrupt request flag. when the ipxxx flag is 1, the interrupt is enabled; when it is 0, the interrupt is disabled. (2) ei/di instruction whether an accepted interrupt is executed or not is specified by the ei or di instruction. when the ei instruction is executed, inte (interrupt enable flag), which enables the interrupt, is set to 1. the inte flag is not registered on the register file. consequently, the status of this flag cannot be checked by an instruction. the di flag clears the inte flag to 0 to disable all the interrupts. the inte flag is also cleared to 0 at reset, disabling all the interrupts. table 7-2. interrupt request flags and interrupt enable flag interrupt signal setting interrupt request flag interrupt request flag enable flag irqtm reset by 8-bit timer. iptm irq set when edge of int pin input signal is detected ip irqbtm reset by basic interval timer. ipbtm 7.2.1 int this flag reads the int pin status. when a high level is input to the int pin, this flag is set to 1; when a low level is input, the flag is reset to 0. 32 10 0 0 0 int address rf : 0fh int on reset undefined r/w r 0 1 int pin level detection int pin : low level int pin : high level
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 51 7.2.2 ieg this pin selects the interrupt edge to be detected on the int pin. when this flag is 0, the interrupt is detected at the rising edge; when it is 1, the interrupt is detected at the falling edge. 32 10 0 0 0 ieg address rf : 1fh ieg on reset 0h r/w r/w 0 1 int pin interrupt detection edge selection rising edge of int pin falling edge of int pin 7.2.3 interrupt enable flag this flag enables each interrupt source. when this flag is 1, the corresponding interrupt is enabled; when it is 0, the interrupt is disabled. 32 10 0 ipbtm ip iptm address rf : 2fh iptm on reset 0h r/w r/w 0 1 8-bit timer interrupt enable flag disables interrupt acceptance by 8-bit timer enables interrupt acceptance by 8-bit timer ip 0 1 int pin interrupt enable flag disables interrupt acceptance by int pin input ipbtm 0 1 basic interval timer interrupt enable flag disables interrupt acceptance by basic interval timer enables interrupt acceptance by basic interval timer enables interrupt acceptance by int pin input
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 52 7.2.4 irq this is an interrupt request flag that indicates the interrupt request status. when an interrupt request is generated, this flag is set to 1. when the interrupt has been accepted, the interrupt request flag is reset to 0. the interrupt request flag can be read or written by the program. therefore, when it is set to 1, an interrupt can be generated by the software. by writing 0 to the flag, the interrupt pending status can be canceled. 32 10 0 0 0 irqbtm address rf : 3dh irqbtm on reset 0h r/w r/w 0 1 basic interval timer interrupt request flag basic interval timer interrupt request has been made. 32 10 0 0 0 irq address rf : 3eh irq on reset 0h r/w r/w 0 1 int pin interrupt request flag interrupt request has not been made. interrupt request has been made at rising edge or falling edge of int input. 32 10 0 0 0 irqtm address rf : 3fh irqtm on reset 1h note r/w r/w 0 1 8-bit timer interrupt request flag 8-bit timer interrupt request has been made. interrupt request has not been made. interrupt request has not been made. note it is also set to 1h after releasing the stop mode.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 53 7.3 interrupt sequence if irq flag is set to 1 when ip flag is 1, interrupt processing is started after the instruction cycle of the instruction executed when irq flag was set has ended. since the movt instruction, ei instruction, and the instruction which matches the condition to skip use two instruction cycles, the interrupt enabled while this instruction is executed is processed after the second instruction cycle is over. if ip flag is 0, the interrupt processing is not performed even if irq flag is set, until ip flag is set. if two or more interrupts are enabled simultaneously, the interrupts are processed starting from the one with the highest priority. the interrupt with the lower priority is kept pending until the processing of the interrupt with the higher priority is finished. 7.3.1 operations when interrupt is accepted when an interrupt has been accepted, the cpu performs processing in the following sequence: clears irq corresponding to inte flag and accepted interrupt decrements value of stack pointer by 1 (sp ?1) saves contents of program counter to stack addressed by stack pointer loads vector address to program counter save contents of psword to interrupt stack register one instruction cycle is required to perform the above processing.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 54 7.3.2 returning from interrupt processing routine to return from an interrupt processing routine, use the reti instruction. then the following processing is executed within an instruction cycle. loads contents of interrupt stack register to psword increments value of stack pointer by 1 loads contents of stack addressed by stack pointer to program counter to enable an interrupt after the processing of an interrupt has been finished, the ei instruction must be executed immediately before the reti instruction. accepting the interrupt is enabled by the ei instruction after the instruction next to the ei instruction has been executed. therefore, the interrupt is not accepted between the ei and reti instructions.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 55 8. standby functions m pd17236 is provided with halt and stop modes as standby functions. by using the standby function, current consumption can be reduced. in the halt mode, the program is not executed, but the system clock f x is not stopped. this mode is main- tained, until the halt mode release condition is satisfied. in the stop mode, the system clock is stopped and program execution is stopped. this mode is maintained, until the stop mode release condition is satisfied. the halt mode is set, when the halt instruction has been executed. the stop mode is set, when the stop instruction has been executed. 8.1 halt mode in this mode, program execution is temporarily stopped, with the main clock continuing oscillating, to reduce current consumption. use the halt instruction to set the halt mode. the halt mode releasing condition can be specified by the operand for the halt instruction, as shown in table 8-1. after the halt mode has been released, the operation is performed as shown in table 8-2 and figure 8-1. caution do not execute an instruction that clears the interrupt request flag (irq ) for which the interrupt enable flag (ip ) is set immediately before the halt 8h instruction; otherwise, the halt mode may not be set. table 8-1. halt mode releasing conditions operand value releasing conditions 0010b (02h) when interrupt request (irqtm) occurs for 8-bit timer <1> when interrupt request (irqtm, irqbtm, or irq), whose interrupt enable flag (iptm, 1000b (08h) ipbtm, or ip) is set, occurs <2> when any of p0a 0 -p0a 3 pins goes low <3> when p0b 0 -p0b 3 , p0c 0 -p0c 3 , and p0d 0 -p0d 3 are used as input pins and any of these goes low other than above setting prohibited table 8-2. operations after halt mode release (1/2) (a) halt 08h halt mode released by: interrupt status interrupt enable flag operations after halt mode release low-level input of p0a 0 -p0a 3 , dont care dont care instruction next to halt is executed p0b 0 -p0b 3 , p0c 0 -p0c 3 , p0d 0 -p0d 3 when release condition is di disabled standby mode is not released satisfied by interrupt enabled instruction next to halt is executed ei disabled standby mode is not released enabled branches to interrupt vector address
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 56 table 8-2. operations after halt mode release (2/2) (b) halt 02h halt mode released by: interrupt status interrupt enable flag operations after halt mode release 8-bit timer di disabled instructions are executed from the enabled instruction next to the halt instruction. ei disabled enabled branches to interrupt vector address 8.2 halt instruction execution conditions the halt instruction can be executed, only under special conditions, as shown in table 8-3, to prevent the program from hangup. if the conditions in table 8-3 are not satisfied, the halt instruction is treated as an nop instruction. table 8-3. halt instruction execution conditions operand value execution conditions 0010b (02h) when all interrupt request flags (irqtm) of 8-bit timer are reset 1000b (08h) <1> when interrupt request flag (irqth, irqbtm, or irq) is reset, corresponding to interrupt whose interrupt enable flag (iptm, ipbtm, or ip) is set <2> when high level is input to all p0a 0 -p0a 3 pins <3> when p0b 0 -p0b 3 , p0c 0 -p0c 3 , and p0d 0 -p0d 3 are used as input pins and any of these goes high other than above setting prohibited
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 57 8.3 stop mode in the stop mode, the system clock (f x ) oscillation is stopped and the program execution is stopped to minimize current consumption. to set the stop mode, use the stop instruction. the stop mode releasing condition can be specified by the stop instruction operand, as shown in table 8-4. after the stop mode has released, the operation is performed as follows: <1> resets irqtm. <2> starts the basic interval timer and watchdog timer (does not reset). <3> resets and starts the 8-bit timer. <4> executes the instruction next to [stop 8h] when the current value of the 8-bit counter coincides with the value of the modulo register (irqtm is set). the m pd17236 oscillator is stopped, when the stop instruction has been executed (i.e., in the stop mode). oscillation is not resumed, until the stop mode is released. after the stop mode has been released, the halt mode is set. set the time required to release the halt mode by using the timer with modulo function. the time that elapses, after the stop mode has been released by occurrence of an interrupt, until an operation mode is set, is shown in the following table. caution do not execute an instruction that clears the interrupt request flag (irq ) for which the interrupt enable flag (ip ) is set immediately before the stop 8h instruction; otherwise, the stop mode may not be set. 8-bit modulo register set value time required to set operation mode (tmm) after stop mode release at 4 mhz 40h 4.160 ms (64 m s 65) ffh 16.384 ms (64 m s 256) caution to set the time required for an operation mode to be set after the stop mode has been released, make sure that sufficient time is allowed for oscillation to stabilize. remark set the 8-bit modulo timer before executing stop instruction. table 8-4. stop mode releasing conditions operand value releasing conditions 1000b (08h) <1> when any of p0a 0 -p0a 3 pins goes low <2> when p0b 0 -p0b 3 , p0c 0 -p0c 3 , and p0d 0 -p0d 3 are used as input pins and any of these goes low <3> if the interrupt request (irq) of an interrupt for which the int pin interrupt enable flag (ip) is set is generated at the rising or falling edge of the int pin other than above setting prohibited
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 58 8.4 stop instruction execution conditions the stop instruction can be executed, only under special conditions, as shown in table 8-5, to prevent the program from hang-up. if the conditions in table 8-5 are not satisfied, the stop instruction is treated as an nop instruction. table 8-5. stop instruction execution conditions operand value execution conditions 1000b (08h) <1> high level input for all p0a 0 -p0a 3 pins <2> when p0b 0 -p0b 3 , p0c 0 -p0c 3 , and p0d 0 -p0d 3 are used as input pins and all pins are high <3> if the int pin interrupt request flag (irq) for an interrupt for which the int pin interrupt enable flag (ip) is set is reset other than above setting prohibited 8.5 releasing standby mode operations for releasing the stop and halt modes will be as shown in figure 8-1. figure 8-1. operations after standby mode release (a) releasing stop mode by interrupt stanby release signal stop instruction wait (time set by tmm) operation mode stop mode halt mode operation mode clock oscillation oscillation stops oscillation (b) releasing halt mode by interrupt halt instruction stanby release signal clock operation mode operation mode halt mode oscillation remark the dotted line indicates the operation to be performed when the interrupt request, releasing the standby mode, has been accepted.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 59 9. reset 9.1 reset by reset signal input when a low-level signal more than 10 m s is input to the reset pin, m pd17236 is reset. when the system is reset, the oscillator circuit remains in the halt mode and then enters an operation mode, like when the stop mode has been released. the wait time, after the reset signal has been removed, is 16.384 ms (f x = 4 mhz). on power application, input the reset signal at least once because the internal circuitry operations are not stable. when m pd17225 is reset, the following initialization takes place: (1) program counter is reset to 0. (2) flags in the register file are initialized to their default values (for the default values, refer to figure 11-1 register files ). (3) the default value (0320h) is written to the data buffer (dbf). (4) the hardware peripherals are initialized. (5) the system clock (f x ) stops oscillation. when the reset pin is made high, the system clock starts oscillating, and the program execution starts from address 0 about 16 ms (at 4 mhz) later. figure 9-1. reset operation by reset input reset wait starts from address 0h (about 16 ms at 4 mhz) operation mode or standby mode halt mode operation mode oscillation stops 9.2 reset by watchdog timer (with reset pin internally pulled down) when the watchdog timer operates during program execution, the reset pin is internally pulled down, and the program counter is reset to 0 (normally, the reset pin is pulled up). if the watchdog timer is not reset for a fixed period of time, the program can be restarted from address 0h. program so that the watchdog timer is reset at intervals of within 340 ms (at f x = 4 mhz) (set the wdtres flag).
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 60 9.3 reset by stack pointer (with reset pin internally pulled down) when the value of the stack pointer reaches 6h or 7h during program execution, the reset pin is internally pulled down, and the program counter is reset to 0 (normally, the reset pin is pulled up). therefore, if an interrupt or call instruction is executed when the value of the stack pointer is 0 (stack underflow) or if the stack level exceeds 6 as a result of execution of the ret instruction because the correspondence between the call and ret instructions is not established (stack overflow), the program can be restarted from address 0h. table 9-1. status of each hardware after reset hardware reset input during reset input standby mode during operation program counter (pc) 0000h 0000h port input/output input input output latch 0 0 data memory (ram) general-purpose data memory retains previous undefined (except dbf, port register) status dbf 0320h 0320h system register (sysreg) 0 0 wr retains previous undefined status control register refer to figure 11-1 register files 8-bit timer counter (tmc) 00h 00h modulo register (tmm) ffh ffh remote controller carrier nrz high-level timer modulo register (nrzhtmm) retains previous undefined generator nrz low-level timer modulo register (nrzltmm) status basic interval timer/watchdog timer counter 00h 00h
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 61 10. low-voltage detector circuit (with reset pin internally pulled down) the reset pin is internally pulled down for initialization (reset) to prevent program hang-up that may take place when the batteries are replaced, if the circuit detects a low voltage. a drop in the supply voltage is detected if the status of v dd = 1.7 to 2.0 v lasts for 1 ms or longer. note, however, that 1 ms is the guaranteed value and that the microcontroller may be reset even if the above low-voltage condition lasts for less than 1 ms. although the voltage at which the the reset function is effected ranges from 1.7 to 2.0 v, the program counter is prevented from hang-up even if the supply voltage drops until the reset function is effected, if the instruction execution time is from 4 to 32 m s. note that some oscillators stop oscillating before the reset function is effected. the low-voltage detector circuit can be set arbitrarily by the mask option.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 62 11. assembler reserved words 11.1 mask option directives when developing the m pd17236 program, mask options must be specified by using mask option directives in the program. to select the pia 0 pin and remote controller carrier generator clock of the m pd17236, a mask option must be specified. 11.1.1 option and endop directives that portion of the program enclosed by the option and endop directives is called a mask option definition block. this block is described in the following format: description format: symbol mnemonic operand comment [label: ] option [;comment] : : : endop 11.1.2 mask option definition directives table 11-1 lists the directives that can be used in the mask option definition block. here is an example of mask option definition: description example: symbol mnemonic operand comment option optp1a0 inp1a0 ; sets p1a 0 pin in input mode optpoc usepoc ; internal low-voltage detector circuit optrfx usefx ; sets clock for carrier generation of remote controller ; carrier generator to f x endop
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 63 table 11-1. mask option definition directives name directive operands 1st operand 2nd operand 3rd operand 4th operand p1a0 optp1a0 1 inp1a0 (sets p1a 0 pin in input mode) outp1a0 (sets p1a 0 pin in output mode) rfx optrfx 1 usefx (sets clock for carrier generation to f x ) usehalfx (sets clock for carrier generation to f x /2) poc optpoc 1 usepoc (low-voltage detector circuit provided) nousepoc (low-voltage detector circuit not provided) 11.2 reserved symbols the symbols defined by the m pd17236 device file are listed in table 11-2. the defined symbols are the following register file names, port names, and peripheral hardware names. 11.2.1 register file the names of the symbols assigned to the register file are defined. these registers are accessed by the peek and poke instructions through the window register (wr). figure 11-1 shows the register file. 11.2.2 registers and ports on data memory the names of the registers assigned at addresses 00h through 7fh on the data memory and the names of ports assigned to address 70h and those that follow, and system register names are defined. figure 11-2 shows the data memory configuration. 11.2.3 peripheral hardware the names of peripheral hardware accessed by the get and put instructions are defined. table 11-3 shows the peripheral hardware.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 64 table 11-2. reserved symbols (1/3) symbol name attribute value r/w description dbf3 mem 0.0ch r/w bits 15-12 of data buffer dbf2 mem 0.0dh r/w bits 11-8 of data buffer dbf1 mem 0.0eh r/w bits 7-4 of data buffer dbf0 mem 0.0fh r/w bits 3-0 of data buffer ar3 mem 0.74h r/w bits 15-12 of address register ar2 mem 0.75h r/w bits 11-8 of address register ar1 mem 0.76h r/w bits 7-4 of address register ar0 mem 0.77h r/w bits 3-0 of address register wr mem 0.78h r/w window register bank mem 0.79h r/w bank register ixh mem 0.7ah r/w index register, high mph mem 0.7ah r/w data memory row address pointer, high mpe flg 0.7ah.3 r/w memory pointer enable flag ixm mem 0.7bh r/w index register, middle mpl mem 0.7bh r/w data memory row address pointer, low ixl mem 0.7ch r/w index register, low rph mem 0.7dh r/w general register pointer, high rpl mem 0.7eh r/w general register pointer, low psw mem 0.7fh r/w program status word bcd flg 0.7eh.0 r/w bcd flag cmp flg 0.7fh.3 r/w compare flag cy flg 0.7fh.2 r/w carry flag z flg 0.7fh.1 r/w zero flag ixe flg 0.7fh.0 r/w index enable flag p0a0 flg 0.70h.0 r/w bit 0 of port 0a p0a1 flg 0.70h.1 r/w bit 1 of port 0a p0a2 flg 0.70h.2 r/w bit 2 of port 0a p0a3 flg 0.70h.3 r/w bit 3 of port 0a p0b0 flg 0.71h.0 r/w bit 0 of port 0b p0b1 flg 0.71h.1 r/w bit 1 of port 0b p0b2 flg 0.71h.2 r/w bit 2 of port 0b p0b3 flg 0.71h.3 r/w bit 3 of port 0b p0c0 flg 0.72h.0 r/w bit 0 of port 0c p0c1 flg 0.72h.1 r/w bit 1 of port 0c p0c2 flg 0.72h.2 r/w bit 2 of port 0c p0c3 flg 0.72h.3 r/w bit 3 of port 0c p0d0 flg 0.73h.0 r/w bit 0 of port 0d p0d1 flg 0.73h.1 r/w bit 1 of port 0d p0d2 flg 0.73h.2 r/w bit 2 of port 0d p0d3 flg 0.73h.3 r/w bit 3 of port 0d
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 65 table 11-2. reserved symbols (2/3) symbol name attribute value r/w description p0e0 flg 0.6fh.0 r/w bit 0 of port 0e p0e1 flg 0.6fh.1 r/w bit 1 of port 0e p0e2 flg 0.6fh.2 r/w bit 2 of port 0e p0e3 flg 0.6fh.3 r/w bit 3 of port 0e p1a0 flg 1.70h.0 r/w bit 0 of port 1a (input or output set by mask option) sp mem 0.81h r/w stack pointer sysck flg 0.82h.0 r/w system clock select flag wdtres flg 0.83h.3 r/w watchdog timer reset flag btmck flg 0.83h.2 r/w basic interval timer mode select flag btmres flg 0.83h.1 r/w basic interval timer mode reset flag int flg 0.8fh.0 r int pin status flag nrzbf flg 0.91h.0 r/w nrz buffer data flag nrz flg 0.92h.0 r/w nrz data flag p0ebpu0 flg 0.97h.0 r/w p0e 0 pull-up setting flag p0ebpu1 flg 0.97h.1 r/w p0e 1 pull-up setting flag p0ebpu2 flg 0.97h.2 r/w p0e 2 pull-up setting flag p0ebpu3 flg 0.97h.3 r/w p0e 3 pull-up setting flag ieg flg 0.9fh.0 r/w int pin interrupt edge flag p0bbio0 flg 00a6h.0 r/w p0b 0 i/o select flag p0bbio1 flg 00a6h.1 r/w p0b 1 i/o select flag p0bbio2 flg 00a6h.2 r/w p0b 2 i/o select flag p0bbio3 flg 00a6h.3 r/w p0b 3 i/o select flag p0ebio0 flg 0.0a7h.0 r/w p0e 0 i/o setting flag p0ebio1 flg 0.0a7h.1 r/w p0e 1 i/o setting flag p0ebio2 flg 0.0a7h.2 r/w p0e 2 i/o setting flag p0ebio3 flg 0.0a7h.3 r/w p0e 3 i/o setting flag ipbtm flg 0.0afh.2 r/w basic interval timer interrupt enable flag ip flg 0.0afh.1 r/w int pin interrupt enable flag iptm flg 0.0afh.0 r/w timer interrupt enable flag tmen flg 0.0b3h.3 r/w timer enable flag tmres flg 0.0b3h.2 r/w timer reset flag tmck1 flg 0.0b3h.1 r/w timer clock flag tmck0 flg 0.0b3h.0 r/w timer clock flag p0cgio flg 00b7h.2 r/w p0c 3 -p0c 0 i/o select flag p0dgio flg 00b7h.3 r/w p0d 3 -p0d 0 i/o select flag irqbtm flg 0.0bdh.0 r/w basic interval timer interrupt request flag irq flg 0.0beh.0 r/w int pin interrupt request flag irqtm flg 0.0bfh.0 r/w timer interrupt request flag tmc dat 05h r timer count register tmm dat 06h w timer modulo register
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 66 table 11-2. reserved symbols (3/3) symbol name attribute value r/w description nrzltmm dat 03h r/w nrz low-level timer modulo register nrzhtmm dat 04h r/w nrz high-level timer modulo register ar dat 40h r/w address register dbf dat 0fh fixed operand value for put, get, movt instruction ix dat 01h fixed operand value for inc instruction
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 67 [memo]
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 68 figure 11-1. register files (1/2) column address row address 01234567 note bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 0 1 0 1 0 0 0 sysck 0 0 0 0 wdtres btmck btmres 0 sp 0 0 0 0 0 0 0 0 0 0 0 nrz 0 0 0 0 0 0 0 nrzbf 0 1 2 3 tmen tmres tmck1 tmck0 1 0 0 0 0 0 0 0 0 0 0 0 p0ebpu3 p0ebpu2 p0ebpu1 p0ebpu0 p0ebio3 p0ebio2 p0ebio1 p0ebio0 note note note note note note note p0bbio3 p0bbio2 p0bbio1 p0bbio0 p0dgio p0cgio 0 0 0 0 0 0 1 1 0 0 note on reset figure 11-2. data memory configuration 0123 4567 89abcdef 0 1 2 3 4 5 6 7 row address system register dbf p0e 0 -p0e 3 dbf3dbf2dbf1dbf0 ar3 ar2 ar1 ar0 wr bank ixh ixm ixl rph rpl psw p0d 0 -p0d 3 column address p0c 0 -p0c 3 p0b 0 -p0b 3 p1a 0 p0a 0 -p0a 3
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 69 figure 11-1. register files (2/2) column address row address 89abcdef bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 p 0 0 0 1 0 0 0 int 0 0 0 irqtm 0 0 0 ieg 0 ipbtm ip iptm 0 0 0 0 0 0 0 irq 0 0 0 0 0 0 0 irqbtm note note note note note note note note note on reset p: when int pin is high level, 1 or when int pin is low level, 0. table 11-3. peripheral hardware name address valid bit description tmc 05h 8 timer count register tmm 06h 8 timer modulo register nrzltmm 03h 8 low-level timer modulo register for nrz nrzhtmm 04h 8 high-level timer modulo register for nrz ar 40h 16 address register
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 70 12. instruction set 12.1 instruction set outline b 15 b 14 -b 11 01 bin. hex. 0 0 0 0 0 add r, m add m, #n4 0 0 0 1 1 sub r, m sub m, #n4 0 0 1 0 2 addc r, m addc m, #n4 0 0 1 1 3 subc r, m subc m, #n4 0 1 0 0 4 and r, m and m, #n4 0 1 0 1 5 xor r, m xor m, #n4 0 1 1 0 6 or r, m or m, #n4 inc ar inc ix movt dbf, @ar br @ar call @ar ret syscal entry note retsk ei di 0 1 1 1 7 reti push ar pop ar get dbf, p put p, dbf peek wr, rf poke rf, wr rorc r stop s halt h nop 1 0 0 0 8 ld r, m st m, r 1 0 0 1 9 ske m, #n4 skge m, #n4 1 0 1 0 a mov @r, m mov m, @r 1 0 1 1 b skne m, #n4 sklt m, #n4 1 1 0 0 c br addr (page 0) call addr 1 1 0 1 d br addr (page 1) mov m, #n4 1 1 1 0 e br addr (page 2) skt m, #n 1 1 1 1 f br addr (page 3) skf m, #n note m pd17234, 17235, 17236 only
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 71 12.2 legend ar : address register asr : address stack register specified by stack pointer addr : program memory address (low-order 11 bits) bank : bank register cmp : compare register cy : carry flag dbf : data buffer entry : entry address of system segment h : halt releasing condition intef : interrupt enable flag intr : register automatically saved to stack in case of interrupt intsk : interrupt stack register ix : index register mp : data memory row address pointer mpe : memory pointer enable flag m : data memory address specified by m r , m c m r : data memory row address (high) m c : data memory column address (low) n : bit position (4 bits) n4 : immediate data (4 bits) page : page (bit 11 and 12 of program counter) pc : program counter p : peripheral address p h : peripheral address (high-order 3 bits) p l : peripheral address (low-order 4 bits) r : general register column address rf : register file address rf r : register file row address (high-order 3 bits) rf c : register file column address (low-order 4 bits) sp : stack pointer s : stop releasing condition wr : window register ( ) : contents addressed by
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 72 12.3 list of instruction sets group mnemonic operand operation instruction code op code operand add r, m (r) ? (r) + (m) 00000 m r m c r m, #n4 (m) ? (m) + n4 10000 m r m c n4 add addc r, m (r) ? (r) + (m) + cy 00010 m r m c r m, #n4 (m) ? (m) + n4 + cy 10010 m r m c n4 inc ar ar ? ar + 1 00111 000 1001 0000 ix ix ? ix + 1 00111 000 1000 0000 sub r, m (r) ? (r) C (m) 00001 m r m c r subtract m, #n4 (m) ? (m) C n4 10001 m r m c n4 subc r, m (r) ? (r) C (m) C cy 00011 m r m c r m, #n4 (m) ? (m) C n4 C cy 10011 m r m c n4 or r, m (r) ? (r) (m) 00110 m r m c r m, #n4 (m) ? (m) n4 10110 m r m c n4 logical and r, m (r) ? (r) (m) 00100 m r m c r m, #n4 (m) ? (m) n4 10100 m r m c n4 xor r, m (r) ? (r) " (m) 00101 m r m c r m, #n4 (m) ? (m) " n4 10101 m r m c n4 judge skt m, #n cmp ? 0, if (m) n = n, then skip 11110 m r m c n skf m, #n cmp ? 0, if (m) n = 0, then skip 11111 m r m c n ske m, #n4 (m) C n4, skip if zero 01001 m r m c n4 compare skne m, #n4 (m) C n4, skip if not zero 01011 m r m c n4 skge m, #n4 (m) C n4, skip if not borrow 11001 m r m c n4 sklt m, #n4 (m) C n4, skip if borrow 11011 m r m c n4 rotate rorc r 00111 000 0111 r ld r, m (r) ? (m) 01000 m r m c r st m, r (m) ? (r) 11000 m r m c r @r, m if mpe = 1 : (mp, (r)) ? (m) 01010 m r m c r if mpe = 0 : (bank, m r , (r)) ? (m) transfer mov m, @r if mpe = 1 : (m) ? (mp, (r)) 11010 m r m c r if mpe = 0 : (m) ? (bank, m r , (r)) m, #n4 (m) ? n4 11101 m r m c n4 movt dbf, sp ? sp C 1, asr ? pc, pc ? ar 00111 000 0001 0000 @ar dbf ? (pc), pc ? asr, sp ? sp + 1 cy ? (r) b3 ? (r) b2 ? (r) b1 ? (r) b0
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 73 group mnemonic operand operation instruction code op code operand push ar sp ? sp C 1, asr ? ar 00111 000 1101 0000 pop ar ar ? asr, sp ? sp + 1 00111 000 1100 0000 transfer peek wr, rf wr ? (rf) 00111 rf r 0011 rf c poke rf, wr (rf) ? wr 00111 rf r 0010 rf c get dbf, p (dbf) ? (p) 00111 p h 1011 p l put p, dbf (p) ? (dbf) 00111 p h 1010 p l branch br addr note 1 note 1 addr @ar pc ? ar 00111 000 0100 0000 addr sp ? sp C 1, asr ? pc, 11100 addr call pc 10C0 ? addr, page ? 0 @ar sp ? sp C 1, asr ? pc, 00111 000 0101 0000 subroutine pc ? ar entry sp ? sp C 1, asr ? pc, sgr ? 1, 00111 entry h 0000 entry l syscal note 2 pc 12,11 ? 0, pc 10C8 ? entry h , pc 7C4 ? 0, pc 3C0 ? entry l ret pc ? asr, sp ? sp + 1 00111 000 1110 0000 retsk pc ? asr, sp ? sp + 1 and skip 00111 001 1110 0000 reti pc ? asr, intr ? intsk, sp ? sp + 1 00111 100 1110 0000 interrupt ei intef ? 1 00111 000 1111 0000 di intef ? 0 00111 001 1111 0000 stop s stop 00111 010 1111 s other halt h halt 00111 011 1111 h nop no operation 00111 100 1111 0000 notes 1. the operation and operation codes br addr of the m pd17230, 17231, 17232, 17233, 17234, 17235, and 17236 are as follows: (a) m pd17230 operand operation op code addr pc 10-0 ? addr 01100 (b) m pd17231 operand operation op code addr pc 10C0 ? addr, page ? 0 01100 pc 10C0 ? addr, page ? 1 01101 (c) m pd17232 operand operation op code addr pc 10C0 ? addr, page ? 0 01100 pc 10C0 ? addr, page ? 1 01101 pc 10C0 ? addr, page ? 2 01110
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 74 (d) m pd17233, 17234, 17235, 17236 operand operation op code addr pc 10C0 ? addr, page ? 0 01100 pc 10C0 ? addr, page ? 1 01101 pc 10C0 ? addr, page ? 2 01110 pc 10C0 ? addr, page ? 3 01111 2. m pd17234, 17235, and 17236 only 12.4 assembler (ra17k) built-in macro instruction legend flag n : flg type symbol n : bit number < > : contents in < > can be omitted mnemonic operand operation n built-in sktn flag 1, ...flag n if (flag 1) to (flag n) = all 1, then skip 1 n 4 macro skfn flag 1, ...flag n if (flag 1) to (flag n) = all 0, then skip 1 n 4 setn flag 1, ...flag n (flag 1) to (flag n) ? 11 n 4 clrn flag 1, ...flag n (flag 1) to (flag n) ? 01 n 4 notn flag 1, ...flag n if (flag n) = 0, then (flag n) ? 1 1 n 4 if (flag n) = 1, then (flag n) ? 0 initflg flag 1, if description = not flag n, then (flag n) ? 0 1 n 4 < flag n> if description = flag n, then (flag n) ? 1 bankn (bank) ? n n = 0, 1 expantion brx label jump label instruction callx function-name call sub-routine initflgx flag 1, if description = not (or inv) n 4 ... flag n flag, (flag) ? 0 if description = flag, (flag) ? 1
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 75 13. electrical specifications absolute maximum ratings (t a = 25 c) item symbol conditions ratings unit supply voltage v dd C0.3 to +3.8 v input voltage v i C0.3 to v dd + 0.3 v output voltage v o C0.3 to v dd + 0.3 v high-level output current note i oh rem pin peak value C36.0 ma rms value C24.0 ma 1 pin (p0e pin) peak value C7.5 ma rms value C5.0 ma total of p0e pins peak value C22.5 ma rms value C15.0 ma low-level output current note i ol 1 pin (p0b, p0c, p0d, peak value 7.5 ma p0e, p1a 0 , rem pins) rms value 5.0 ma total of p0b, p0c, p0d, peak value 22.5 ma p1a 0 , rem pins rms value 15.0 ma total of p0e pins peak value 30.0 ma rms value 20.0 ma operating temperature t a C40 to +85 c storage temperature t stg C65 to +150 c power dissipation p d t a = 85 c 180 mw note calculate rms value by this expression: [rms value] = [peak value] ? duty caution even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. the absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. be sure not to exceed or fall below this value when using the product.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 76 recommended operating ranges (t a = C40 to +85 c, v dd = 2.0 to 3.6 v) item symbol conditions min. typ. max. unit supply voltage v dd1 f x = 1 mhz high-speed mode 2.0 3.0 3.6 v (instruction execution time: 16 m s) v dd2 f x = 4 mhz ordinary mode (instruction execution time: 4 m s) v dd3 f x = 8 mhz high-speed mode (instruction execution time: 4 m s) v dd4 high-speed mode 2.2 3.0 3.6 v (instruction execution time: 2 m s) oscillation frequency f x 1.0 4.0 8.0 mhz operating temperature t a C40 +25 +85 c low-voltage detector circuit note t cy 432 m s (mask option) note reset if the status of v dd = 1.7 to 2.0 v lasts for 1 ms or longer. program hang-up does not occur even if the voltage drops, until the reset function is effected. some oscillators stop oscillating before the reset function is effected. remark the region indicated by the broken line in the above figure is the guaranteed operating range in the high- speed mode. f x vs v dd supply voltage: v dd (v) 0.4 2 1 3 4 5 6 7 8 9 10 2 0 2.2 3 3.6 4 (ordinary mode) system clock: f x (mhz) (mh z ) operation guaranteed area
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 77 system clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.0 to 3.6 v) resonator recommended item conditions min. typ. max. unit constants ceramic oscillation frequency 1.0 4.0 8.0 mhz resonator (f x ) note 1 oscillation after v dd reached min. 4 ms stabilization time note 2 in oscillation voltage range notes 1. the oscillation frequency only indicates the oscillator characteristics. 2. the oscillation stabilization time is necessary for oscillation to be stabilized, after v dd application or stop mode release. caution to use a system clock oscillator circuit, perform the wiring in the area enclosed by the dotted line in the above figure as follows, to avoid adverse wiring capacitance influences: ? keep wiring length as short as possible. ? do not cross a signal line with some other signal lines. do not route the wiring in the vicinity of lines through which a large current flows. ? always keep the oscillator circuit capacitor ground at the same potential as gnd. do not ground the capacitor to a ground pattern, through which a large current flows. ? do not extract signals from the oscillator circuit. external circuit example x in x out x in x out r1 c2 c1
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 78 recommended oscillator constants system clock: ceramic resonator (t a = C40 to +85 c) manufacturer part number frequency recommended circuit oscillation voltage remark (mhz) constants (pf) range (v dd ) c1 c2 min. (v) max. (v) tdk corp. fcr4.0mc5 4.0 C C 2.0 3.6 fcr6.0mc5 6.0 C C 2.2 fcr8.0mc5 8.0 C C caution the oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. if the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. for this, it is necessary to directly contact the manufacturer of the resonator being used.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 79 dc characteristics (t a = C40 to +85 c, v dd = 2.0 to 3.6 v) item symbol conditions min. typ. max. unit high-level input voltage v ihi1 p1a 0 (input), reset, int 0.80v dd v dd v v ih2 p0a, p0b, p0c, p0d 0.70v dd v dd v v ih3 p0e 0.80v dd v dd v low-level input voltage v il1 p1a 0 (input), reset, int 0 0.2 v dd v v il2 p0a, p0b, p0c, p0d 0 0.3 v dd v v il3 p0e 0 0.35 v dd v high-level input leakage i lih p0a, p0b, p0c, p0d, p0e, v ih = v dd 3.0 m a current p1a 0 , reset, int low-level input leakage i lil1 int v il = 0 v C3.0 m a current i lil2 p0e, reset v il = 0 v C3.0 m a w/o pull-up resistor internal pull-up resistor r 1 p0e, reset (pulled up) 25 50 100 k w r 2 p0a, p0b, p0c, p0d 100 200 400 k w r 3 reset (pulled down) 2.5 5 10 k w high-level output current i oh rem v oh = 1.0 v, C6 C13 C24 ma v dd = 3 v high-level output voltage v oh p0e, rem i oh = C0.5 ma v dd C0.3 v dd v low-level output voltage v ol1 p0b, p0c, p0d, p1a 0 (output), rem i ol = 0.5 ma 0 0.3 v v ol2 p0e i ol = 1.5 ma 0 0.3 v data retention characteristics v dddr reset = low level or stop mode 1.3 3.6 v low-voltage detection v dt reset pin pulled down, v dt = v dd 1.70 1.85 2.0 v voltage (mask option) poc detection pulse width t dt v dd < v dt 1ms supply current i dd1 operating mode v dd = 3 v 10% f x = 1 mhz 0.6 1.1 ma (high-speed) f x = 4 mhz 0.75 1.3 ma f x = 8 mhz 0.9 1.6 ma i dd2 operating mode v dd = 3 v 10% f x = 1 mhz 0.48 0.9 ma (low-speed) f x = 4 mhz 0.6 1.1 ma f x = 8 mhz 0.8 1.4 ma i dd3 halt mode v dd = 3 v 10% f x = 1 mhz 0.4 0.75 ma f x = 4 mhz 0.45 0.85 ma f x = 8 mhz 0.5 0.95 ma i dd4 stop mode v dd = 3 v 10% 2.0 20.0 m a built-in poc t a = 25 c 2.0 5.0 m a
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 80 ac characteristics (t a = C40 to +85 c, v dd = 2.0 to 3.6 v) item symbol conditions min. typ. max. unit cpu clock cycle time note t cy1 3.8 33 m s (instruction execution time) t cy2 v dd = 2.2 to 3.6 v 1.9 33 m s int high/low level width t inth, 20 m s t intl reset low level width t rsl 10 m s note the cpu clock cycle time (instruction execution time) is determined by the oscillation frequency of the reso- nator connected and sysck (rf: address 02h) of the register file. the figure on the right shows the cpu clock cycle time t cy vs. supply voltage v dd characteristics (refer to 4. clock generator circuit ). t cy vs v dd supply voltage v dd (v) 2 1 3 4 5 6 7 8 9 10 33 40 2 01 3 4 cpu clock cycle time tc y ( s) 3.8 1.9 2.2 3.6 operation guaranteed area m
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 81 14. application circuit example ? m pd17235gt-xxx, 17236gt-xxx 128 227 326 425 524 623 722 821 920 10 19 11 18 12 17 13 16 14 15 p0d 2 p0d 3 int p0e 0 p0e 1 p0e 2 p0e 3 rem p0d 1 p0d 0 p0c 3 p0c 2 p0c 1 p0c 0 p0b 3 p0b 2 p0b 1 p0b 0 p0a 3 p0a 2 p0a 1 p0a 0 v dd x out x in gnd reset p1a 0 3 v 4 mhz remarks 1. in the above circuit example, p1a 0 is set in the output mode by mask option. 2. the above example is for the 28-pin plastic sop (375 mil). with the 30-pin plastic shrink sop (300 mil), open ic1 (pin 15) and ic2 (pin 30).
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 82 15. package drawings 114 28 15 s s 28-pin plastic sop (375 mil) item millimeters a b c e f g h i j 17.9 0.17 1.27 (t.p.) 2.6 0.2 2.50 10.3 0.3 0.78 max. 0.12 1.6 0.2 7.2 0.2 m 0.1 0.1 n p28gm-50-375b-4 p3 + 7 note each lead centerline is located within 0.12 mm of its true position (t.p.) at maximum material condition. d 0.42 + 0.08 - 0.07 k 0.17 + 0.08 - 0.07 l 0.8 0.2 0.15 - 3 detail of lead end m c m n a b h k l p j i g d e f
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 83 s s h j t i g d e f c b k p l u n item millimeters b c i 0.65 (t.p.) 0.45 max. l 0.13 0.5 6.1 0.2 m 0.10 n 30 pin plastic ssop (300 mil) a 9.85 0.15 k 0.17 0.03 note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. d 0.1 0.05 0.24 e 1.3 0.1 f g h 8.1 0.2 1.2 + 0.08 - 0.07 j 1.0 0.2 s30mc-65-5a4-1 p3 + 5 - 3 30 16 115 a detail of lead end m m 0.25 t 0.6 0.15 u
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 84 16. recommended soldering conditions for the m pd17236 soldering must be performed under the following conditions. for details of recommended conditions for surface mounting, refer to information document "semiconductor device mounting technology manual" (c10535e) . for other soldering methods, please consult with nec personnel. table 16-1. soldering conditions of surface mount type (1) m pd17235gt- : 28-pin plastic sop (375 mil) m pd17236gt- : 28-pin plastic sop (375 mil) soldering method soldering conditions symbol infrated reflow package peak temperature: 235 c, time: 30 seconds max. (210 c min.), ir35-00-2 number of times: 2 max. vps package peak temperature: 215 c, time: 40 seconds max. (200 c min.), vp15-00-2 number of times: 2 max. wave soldering solder bath temperature: 260 c max, time: 10 seconds max., number of times: ws66-00-1 once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per side of device) caution do not use two or more soldering methods in combination (except the partial heating method). (2) m pd17230mc- -5a4: 30-pin plastic shrink sop (300 mil) m pd17231mc- -5a4: 30-pin plastic shrink sop (300 mil) m pd17232mc- -5a4: 30-pin plastic shrink sop (300 mil) m pd17233mc- -5a4: 30-pin plastic shrink sop (300 mil) m pd17234mc- -5a4: 30-pin plastic shrink sop (300 mil) m pd17235mc- -5a4: 30-pin plastic shrink sop (300 mil) m pd17236mc- -5a4: 30-pin plastic shrink sop (300 mil) soldering method soldering conditions symbol infrated reflow package peak temperature: 235 c, time: 30 seconds max. (210 c min.), ir35-00-3 number of times: 3 max. vps package peak temperature: 215 c, time: 40 seconds max. (200 c min.), vp15-00-3 number of times: 3 max. wave soldering solder bath temperature: 260 c max, time: 10 seconds max., number of times: ws66-00-1 once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per side of device) caution do not use two or more soldering methods in combination (except the partial heating method).
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 85 appendix a. differences between m pd17236 and m pd17p236 m pd17p236 is equipped with prom to which data can be written by the user instead of the internal mask rom (program memory) of the m pd17236. table a-1 shows the differences between the m pd17236 and m pd17p236. the cpu functions and internal hardware of the m pd17p236, 17230, 17231, 17232, 17233, 17234, 17235, and 17236 are identical. therefore, the m pd17p236 can be used to evaluate the program developed for the m pd17231, 17232, 17233, 17234, 17235, and 17236 system. note, however, that some of the electrical specifications such as supply current and low-voltage detection voltage of the m pd17p236 are different from those of the m pd17231, 17232, 17233, 17234, 17235, and 17236. table a-1. differences among m pd17236 and m pd17p236 product name m pd17p236 m pd17236 m pd17p236m1, 17p236m2, item 17p236m3, 17p236m4 program memory one-time prom mask rom 32k bytes (16384 16) (0000h-3fffh) data memory 223 4 bits input/output of p1a 0 pin ? input ( m pd17p236m2, 17p236m4) any (mask option) ? output ( m pd17p236m1, 17p236m3) clock selection for carrier generation ? rf x = f x /2 ( m pd17p236m1, 17p236m2) any (mask option) ? rf x = f x ( m pd17p236m3, 17p236m4) low-voltage detection circuit provided any (mask option) v pp pin, operation mode select pin provided not provided instruction execution time ? 2 m s (v dd = 3.0 to 3.6 v) ? 2 m s (v dd = 2.2 to 3.6 v) ? 4 m s (v dd = 2.2 to 3.6 v) ? 4 m s (v dd = 2.0 to 3.6 v) supply voltage v dd = 2.2 to 3.6 v v dd = 2.0 to 3.6 v packag ? 28-pin plastic sop (375 mil) ? 30-pin plastic shrink sop (300 mil) note although the circuit configuration is identical, its electrical characteristics differ depending on the product.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 86 appendix b. functional comparison of m pd17236 subseries related products product name m pd17201a m pd17207 m pd17202a m pd17215 m pd17216 m pd17217 m pd17218 item rom capacity (bit) 3072 16 4096 16 2048 16 4096 16 6144 16 8192 16 ram capacity (bit) 336 4 112 4 111 4 223 4 lcd controller/driver 136 segments max. 96 segments not provided max. infrared remote controller led output is high-active led output provided (without led output) carrier generator (rem) is low-active i/o ports 19 lines 16 lines 20 lines external interrupt (int) 1 line 1 line (rising-edge, falling-edge detection) (rising-edge detection) analog input 4 channels (8-bit a/d) not provided timer 2 channels 8-bit timer 2 channels 8-bit timer watch timer basic interval timer watchdog timer provided (wdout output) low-voltage detector circuit note not provided provided (wdout output) serial interface 1 channel not provided stack 5 levels (3 levels for multiplexed interrupt) instruction main system 4 m s (4 mhz: with ceramic or ? 2 m s (8 mhz ceramic resonator: execution time clock crystal resonator, in high-speed mode, v dd = 3.5 to 5.5 v) v dd = 2.2 to 5.5 v) ? 4 m s (4 mhz ceramic resonator: in high-speed mode, v dd = 2.2 to 5.5 v) ?8 m s (2 mhz ceramic resonator: in high-speed mode, v dd = 2.0 to 5.5 v) subsystem 488 m s (32.768 khz: with crystal not provided clock resonator, v dd = 2.0 to 5.5 v) supply voltage v dd = 2.2 to 5.5 v (v dd = 2.0 to 5.5 v) v dd = 2.0 to 5.5 v (with subsystem clock) standby function stop, halt package 80-pin plastic qfp 64-pin 28-pin plastic sop plastic qfp 28-pin plastic shrink dip one-time prom products m pd17p207 m pd17p202a m pd17p218 note note that although all the products have the same circuit construction, the electrical specifications differ dependant on each product. ? ?
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 87 m pd17225 m pd17226 m pd17227 m pd17228 m pd17230 m pd17231 m pd17232 m pd17233 m pd17234 m pd17235 m pd17236 2048 16 4096 16 6144 16 8192 16 2048 16 4096 16 6144 16 8192 16 10240 16 12288 16 16384 16 111 4 223 4 not provided provided (without led output) 20 pins 21 pins 1 pin (rising edge, falling edge detection) not provided 2 channels 8-bit timer basic interval timer provided (wdout output) provided provided (wdout output) provided not provided 5 levels (3 nesting levels) ?2 m s (8-mhz ceramic resonator: in high-speed mode, v dd = 2.2 to 3.6 v) ?4 m s (4-mhz ceramic resonator: in high-speed mode, v dd = 2.0 to 3.6 v) not provided v dd = 2.0 to 3.6 v stop, halt 28-pin plastic sop 30-pin plastic shrink sop 28-pin plastic shrink sop 28-pin plastic shrink dip 30-pin plastic shrink sop 30-pin plastic shrink sop m pd17p228 m pd17p236 ?
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 88 appendix c. development tools to develop the programs for the m pd17235 subseries, the following development tools are available: hardware name remarks ie-17k and ie-17k-et are the in-circuit emulators used in common with the 17k series microcontroller. ie-17k and ie-17k-et are connected to a pc-9800 series or ibm pc/at tm compatible machines as the host machine with rs-232c. by using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. a higher level debugging environment can be provided by using man-machine interface simplehost tm . se board this is an se board for m pd17236 subseries. it can be used alone to evaluate a system (se-17235) or in combination with an in-circuit emulator for debugging. emulation probe ep-17k28gt is an emulation probe for 17k series 28-pin sop (gm-3756). when used with (ep-17k28gt) ev-9500gt-28 note 2 , it connects an se board to the target system. emulation probe ep-17k30gs is an emulation probe for 17k series 30-pin shrink sop (mc-5a4). when used (ep-17k30gs) with ev-9500gt-30 note 3 , it connects an se board to the target system. conversion adapter ev-9500gt-28 is a conversion adapter for 28-pin sop (375 mil) and is used to connect (ev-9500gt-28 note 2 ) ep-17k28gt to the target system. conversion adapter the ev-9500gt-30 is a conversion adapter for the 30-pin shrink sop (300 mil). it is used (ev-9500gt-30 note 3 ) to connect the ep-17k30gs and target system. prom programmer af-9706, af-9708, and af-9709 are prom programmers corresponding to m pd17p236. (af-9706 note 4 , af-9708 note 4 , by connecting program adapter pa-17p236 to this prom programmer, m pd17p236 can be af-9709 note 4 ) programmed. program adapter pa-17p236 are adapters that is used to program m pd17p236, and is used in combination (pa-17p236) with af-9706, af-9708, or af-9709. notes 1. low-cost model: external power supply type 2. two ev-9500gt-28s are supplied with the ep-17k28gt. five ev-9500gt-28s are optionally available as a set. 3. two ev-9500gt-30 are supplied with the ep-17k30gs. five ev-9500gt-30s are optionally available as a set. 4. these are products from ando electric co., ltd. for details, consult ando electric co., ltd. (tel: 03-3733- 1166). in-circuit emulator ie-17k, ie-17k-et note 1
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 89 software name outline host machine os supply order code 17k assembler pc-9800 japanese windows tm 3.5" 2hd m saa13ra17k (ra17k) series ibm pc/at japanese windows 3.5" 2hc m sab13ra17k compatible machine english windows m sbb13ra17k 17k series pc-9800 japanese windows 3.5 2hd m saa13cc17k c-like compiler series ( emlc-17k tm ) ibm pc/at japanese windows 3.5 2hc m sab13cc17k compatible machine english windows m sbb13cc17k device file pc-9800 japanese windows 3.5" 2hd m saa13as17235 (as17235) series ibm pc/at japanese windows 3.5" 2hc m sab13as17235 compatible machine english windows m sbb13as17235 support pc-9800 japanese windows 3.5" 2hd m saa13id17k software series ( simplehost ) ibm pc/at japanese windows 3.5" 2hc m sab13id17k compatible machine english windows m sbb13id17k the ra17k is an assembler com- mon to the 17k series products. when developing the program of devices, ra17k is used in combi- nation with a device file (as17225). the emlc-17k is a c-like compiler common to the 17k series. used in combination with the ra17k. the as17235 is a device file for m pd17230, 17231, 17232, 17233, 17234, 17235, and 17236 respec- tively, and are used in combination with an assembler for the 17k se- ries (ra17k). simplehost is a software pack- age that enables man-machine in- terface on the windows when a pro- gram is developed by using an in- circuit emulator and a personal com- puter.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 90 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
data sheet u14360ej1v0ds00 m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 91 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j99.1
emlc-17k and simplehost are trademarks of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of ibm corporation. m pd17230, 17231, 17232, 17233, 17234, 17235, 17236 the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98.8 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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